From: Andrew Jeffery <andrew@aj.id.au>
To: linux-mmc@vger.kernel.org
Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, joel@jms.id.au,
adrian.hunter@intel.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, ryan_chen@aspeedtech.com
Subject: [PATCH v6 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning
Date: Fri, 18 Dec 2020 14:23:32 +1030 [thread overview]
Message-ID: <20201218035338.1130849-1-andrew@aj.id.au> (raw)
Hello,
This series implements support for the MMC core clk-phase-* devicetree bindings
in the Aspeed SD/eMMC driver. The relevant register was exposed on the AST2600
and is present for both the SD/MMC controller and the dedicated eMMC
controller.
v6 simply removes the typedef from v5 in favour of a struct containing the
phase array.
I've just done a quick build test of v6 given the small change and more
extensive testing done with v5.
v5 can be found here:
https://lore.kernel.org/linux-mmc/20201208012615.2717412-1-andrew@aj.id.au/
Please review!
Cheers,
Andrew
Andrew Jeffery (6):
mmc: core: Add helper for parsing clock phase properties
mmc: sdhci-of-aspeed: Expose clock phase controls
mmc: sdhci-of-aspeed: Add AST2600 bus clock support
mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations
MAINTAINERS: Add entry for the ASPEED SD/MMC driver
ARM: dts: rainier: Add eMMC clock phase compensation
MAINTAINERS | 9 +
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 1 +
drivers/mmc/core/host.c | 44 ++++
drivers/mmc/host/Kconfig | 14 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-of-aspeed-test.c | 100 ++++++++
drivers/mmc/host/sdhci-of-aspeed.c | 251 ++++++++++++++++++-
include/linux/mmc/host.h | 13 +
8 files changed, 422 insertions(+), 11 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-of-aspeed-test.c
--
2.27.0
next reply other threads:[~2020-12-18 3:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-18 3:53 Andrew Jeffery [this message]
2020-12-18 3:53 ` [PATCH v6 1/6] mmc: core: Add helper for parsing clock phase properties Andrew Jeffery
2020-12-18 3:53 ` [PATCH v6 2/6] mmc: sdhci-of-aspeed: Expose clock phase controls Andrew Jeffery
2020-12-18 3:53 ` [PATCH v6 3/6] mmc: sdhci-of-aspeed: Add AST2600 bus clock support Andrew Jeffery
2020-12-18 3:53 ` [PATCH v6 4/6] mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations Andrew Jeffery
2021-01-05 13:47 ` Adrian Hunter
2021-01-11 0:02 ` Andrew Jeffery
2020-12-18 3:53 ` [PATCH v6 5/6] MAINTAINERS: Add entry for the ASPEED SD/MMC driver Andrew Jeffery
2020-12-18 3:53 ` [PATCH v6 6/6] ARM: dts: rainier: Add eMMC clock phase compensation Andrew Jeffery
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201218035338.1130849-1-andrew@aj.id.au \
--to=andrew@aj.id.au \
--cc=adrian.hunter@intel.com \
--cc=devicetree@vger.kernel.org \
--cc=joel@jms.id.au \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-aspeed@lists.ozlabs.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=ryan_chen@aspeedtech.com \
--cc=ulf.hansson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox