From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Konrad Dybcio <konrad.dybcio@somainline.org>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
jassisinghbrar@gmail.com, viresh.kumar@linaro.org,
ulf.hansson@linaro.org, bjorn.andersson@linaro.org,
agross@kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 4/5] clk: qcom: Add A7 PLL support
Date: Fri, 8 Jan 2021 16:44:48 +0530 [thread overview]
Message-ID: <20210108111448.GA74017@thinkpad> (raw)
In-Reply-To: <a880d96f-d879-52d0-48ff-cbcdb88a3f29@somainline.org>
On Mon, Jan 04, 2021 at 04:30:11PM +0100, Konrad Dybcio wrote:
> Hi,
>
> could you explicitly state in the probe function (or just in the driver in general, as there's not much more?) and the config structs that the target SoC is X55?
>
The compatible says it...
> A few more SoCs (MDM9607, MSM8x26 and some others) also use what's known as "A7PLL" downstream, but all of them have a separate configuration for their specific PLLs, which aren't compatible with each other.
>
Yes, but that difference can be factored using the SoC specific compatibles in
future. The idea here is to have a generic A7 PLL driver much like A53 one and
use SoC specific PLL settings.
Thanks,
Mani
>
> Konrad
>
next prev parent reply other threads:[~2021-01-08 11:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-04 8:11 [PATCH 0/5] Add APCS support for SDX55 Manivannan Sadhasivam
2021-01-04 8:11 ` [PATCH 1/5] dt-bindings: mailbox: Add binding for SDX55 APCS Manivannan Sadhasivam
2021-01-04 8:11 ` [PATCH 2/5] mailbox: qcom: Add support for SDX55 APCS IPC Manivannan Sadhasivam
2021-01-04 8:11 ` [PATCH 3/5] dt-bindings: clock: Add Qualcomm A7 PLL binding Manivannan Sadhasivam
2021-01-04 8:11 ` [PATCH 4/5] clk: qcom: Add A7 PLL support Manivannan Sadhasivam
2021-01-04 15:30 ` Konrad Dybcio
2021-01-08 11:14 ` Manivannan Sadhasivam [this message]
2021-01-04 8:11 ` [PATCH 5/5] clk: qcom: Add SDX55 APCS clock controller support Manivannan Sadhasivam
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