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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id f201sm176766oig.21.2021.01.12.19.27.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 19:27:53 -0800 (PST) Received: (nullmailer pid 1475163 invoked by uid 1000); Wed, 13 Jan 2021 03:27:52 -0000 Date: Tue, 12 Jan 2021 21:27:52 -0600 From: Rob Herring To: Manivannan Sadhasivam Cc: mturquette@baylibre.com, sboyd@kernel.org, jassisinghbrar@gmail.com, viresh.kumar@linaro.org, ulf.hansson@linaro.org, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/5] dt-bindings: mailbox: Add binding for SDX55 APCS Message-ID: <20210113032752.GA1472520@robh.at.kernel.org> References: <20210108113233.75418-1-manivannan.sadhasivam@linaro.org> <20210108113233.75418-2-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210108113233.75418-2-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 08, 2021 at 05:02:29PM +0530, Manivannan Sadhasivam wrote: > Add devicetree YAML binding for SDX55 APCS GCC block. The APCS block > acts as the mailbox controller and also provides a clock output and > takes 3 clock sources (pll, aux, ref) as input. > > Signed-off-by: Manivannan Sadhasivam > --- > .../mailbox/qcom,apcs-kpss-global.yaml | 59 ++++++++++++++++--- > 1 file changed, 50 insertions(+), 9 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml > index ffd09b664ff5..3c75ea0b6040 100644 > --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml > +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml > @@ -27,26 +27,24 @@ properties: > - qcom,sdm660-apcs-hmss-global > - qcom,sdm845-apss-shared > - qcom,sm8150-apss-shared > + - qcom,sdx55-apcs-gcc > > reg: > maxItems: 1 > > - clocks: > - description: phandles to the parent clocks of the clock driver > - items: > - - description: primary pll parent of the clock driver > - - description: auxiliary parent Keep this here and add the 3rd item and: minItems: 2 Then the if/then can just restrict things to 2 or 3 items. > - > '#mbox-cells': > const: 1 > > '#clock-cells': > const: 0 > > + clocks: > + minItems: 2 > + maxItems: 3 > + > clock-names: > - items: > - - const: pll > - - const: aux > + minItems: 2 > + maxItems: 3 > > required: > - compatible > @@ -55,6 +53,49 @@ required: > > additionalProperties: false > > +allOf: > + - if: > + properties: > + compatible: > + enum: > + - qcom,ipq6018-apcs-apps-global > + - qcom,ipq8074-apcs-apps-global > + - qcom,msm8916-apcs-kpss-global > + - qcom,msm8994-apcs-kpss-global > + - qcom,msm8996-apcs-hmss-global > + - qcom,msm8998-apcs-hmss-global > + - qcom,qcs404-apcs-apps-global > + - qcom,sc7180-apss-shared > + - qcom,sdm660-apcs-hmss-global > + - qcom,sdm845-apss-shared > + - qcom,sm8150-apss-shared > + then: > + properties: > + clocks: > + items: > + - description: Primary PLL parent of the clock driver > + - description: Auxiliary parent > + clock-names: > + items: > + - const: pll > + - const: aux > + - if: > + properties: > + compatible: > + enum: > + - qcom,sdx55-apcs-gcc > + then: > + properties: > + clocks: > + items: > + - description: Primary PLL parent of the clock driver > + - description: Auxiliary parent > + - description: Reference clock > + clock-names: > + items: > + - const: pll > + - const: aux > + - const: ref > examples: > > # Example apcs with msm8996 > -- > 2.25.1 >