From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BECB0C433E0 for ; Wed, 20 Jan 2021 18:42:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7AFBD23406 for ; Wed, 20 Jan 2021 18:42:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404649AbhATSZ5 (ORCPT ); Wed, 20 Jan 2021 13:25:57 -0500 Received: from mail.kernel.org ([198.145.29.99]:47364 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391968AbhATSSy (ORCPT ); Wed, 20 Jan 2021 13:18:54 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id E69E3233ED; Wed, 20 Jan 2021 18:18:10 +0000 (UTC) Date: Wed, 20 Jan 2021 18:18:08 +0000 From: Catalin Marinas To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, Will Deacon , Mark Rutland , David Brazdil , Alexandru Elisei , Ard Biesheuvel , Jing Zhang , Ajay Patil , Prasad Sodagudi , Srinivas Ramana , James Morse , Julien Thierry , Suzuki K Poulose , kernel-team@android.com Subject: Re: [PATCH v4 02/21] arm64: Fix outdated TCR setup comment Message-ID: <20210120181807.GB17952@gaia> References: <20210118094533.2874082-1-maz@kernel.org> <20210118094533.2874082-3-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210118094533.2874082-3-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 18, 2021 at 09:45:14AM +0000, Marc Zyngier wrote: > The arm64 kernel has long be able to use more than 39bit VAs. > Since day one, actually. Let's rewrite the offending comment. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/mm/proc.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 1f7ee8c8b7b8..ece785477bdc 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -464,8 +464,8 @@ SYM_FUNC_START(__cpu_setup) > #endif > msr mair_el1, x5 > /* > - * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for > - * both user and kernel. > + * Set/prepare TCR and TTBR. TCR_EL1.T1SZ gets further > + * adjusted if the kernel is compiled with 52bit VA support. I think both T0SZ and T1SZ get updated based on a mismatch between the kernel configuration and the hardware support. Anyway, I'm not asking for a detailed comment here, so: Acked-by: Catalin Marinas