From: Boris Brezillon <boris.brezillon@collabora.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, richard@nod.at
Cc: Miquel Raynal <miquel.raynal@bootlin.com>,
vigneshr@ti.com, linux-mtd@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
bjorn.andersson@linaro.org
Subject: Re: [PATCH] mtd: rawnand: Do not check for bad block if bbt is unavailable
Date: Wed, 3 Feb 2021 12:24:22 +0100 [thread overview]
Message-ID: <20210203122422.6963b0ed@collabora.com> (raw)
In-Reply-To: <8A2468D5-B435-4923-BA4F-7BF7CC0FF207@linaro.org>
On Wed, 03 Feb 2021 16:22:42 +0530
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> On 3 February 2021 3:49:14 PM IST, Boris Brezillon <boris.brezillon@collabora.com> wrote:
> >On Wed, 03 Feb 2021 15:42:02 +0530
> >Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> >
> >> >>
> >> >> I got more information from the vendor, Telit. The access to the
> >3rd
> >> >partition is protected by Trustzone and any access in non privileged
> >> >mode (where Linux kernel runs) causes kernel panic and the device
> >> >reboots.
> >
> >Out of curiosity, is it a per-CS-line thing or is this section
> >protected on all CS?
> >
>
> Sorry, I didn't get your question.
The qcom controller can handle several chips, each connected through a
different CS (chip-select) line, right? I'm wondering if the firmware
running in secure mode has the ability to block access for a specific
CS line or if all CS lines have the same constraint. That will impact
the way you describe it in your DT (in one case the secure-region
property should be under the controller node, in the other case it
should be under the NAND chip node).
next prev parent reply other threads:[~2021-02-03 11:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-30 3:54 [PATCH] mtd: rawnand: Do not check for bad block if bbt is unavailable Manivannan Sadhasivam
2021-02-01 14:18 ` Miquel Raynal
2021-02-02 4:16 ` Manivannan Sadhasivam
2021-02-02 8:14 ` Miquel Raynal
2021-02-03 9:58 ` Manivannan Sadhasivam
2021-02-03 10:05 ` Miquel Raynal
2021-02-03 10:12 ` Manivannan Sadhasivam
2021-02-03 10:19 ` Boris Brezillon
2021-02-03 10:52 ` Manivannan Sadhasivam
2021-02-03 11:24 ` Boris Brezillon [this message]
2021-02-03 11:41 ` Manivannan Sadhasivam
2021-02-04 8:13 ` Miquel Raynal
2021-02-04 8:52 ` Manivannan Sadhasivam
2021-02-04 8:59 ` Boris Brezillon
2021-02-04 9:04 ` Miquel Raynal
2021-02-04 9:27 ` Boris Brezillon
2021-02-04 9:31 ` Miquel Raynal
2021-02-04 8:59 ` Miquel Raynal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210203122422.6963b0ed@collabora.com \
--to=boris.brezillon@collabora.com \
--cc=bjorn.andersson@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=miquel.raynal@bootlin.com \
--cc=richard@nod.at \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox