From: Miquel Raynal <miquel.raynal@bootlin.com>
To: mdalam@codeaurora.org
Cc: richard@nod.at, vigneshr@ti.com, boris.brezillon@collabora.com,
manivannan.sadhasivam@linaro.org, linux-mtd@lists.infradead.org,
linux-kernel@vger.kernel.org, sricharan@codeaurora.org
Subject: Re: [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset
Date: Fri, 5 Feb 2021 19:01:06 +0100 [thread overview]
Message-ID: <20210205190106.58bf14dd@xps13> (raw)
In-Reply-To: <7ca35f62c4d3ba7833e192cab3a2701d@codeaurora.org>
Hello,
mdalam@codeaurora.org wrote on Fri, 05 Feb 2021 23:26:33 +0530:
> On 2021-01-31 01:37, Md Sadre Alam wrote:
> > This change will remove unused register name macro NAND_DEV1_ECC_CFG.
> > Since this register was only available in QPIC version 1.4.20 ipq40xx
> > and it was not used. In QPIC version 1.5 on wards this register got
> > removed.In QPIC version 2.0 0x2c offset is updated with register
> > NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
> > with offset 0x2c.
> >
> > Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>
> Ping! Is any additional info needed for this patch ?
The patch is fine but we are at -rc6, the NAND PR has already been
sent, I don't plan to add more patches for this release. I will apply
new patches at v5.12-rc1.
Thanks,
Miquèl
next prev parent reply other threads:[~2021-02-05 18:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-30 20:07 [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset Md Sadre Alam
2021-02-05 17:56 ` mdalam
2021-02-05 18:01 ` Miquel Raynal [this message]
2021-02-10 8:58 ` Manivannan Sadhasivam
2021-03-02 16:33 ` Miquel Raynal
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