From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D518CC433DB for ; Mon, 8 Feb 2021 11:31:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D22764EA4 for ; Mon, 8 Feb 2021 11:31:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233236AbhBHLbH (ORCPT ); Mon, 8 Feb 2021 06:31:07 -0500 Received: from mga01.intel.com ([192.55.52.88]:16870 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232978AbhBHLPH (ORCPT ); Mon, 8 Feb 2021 06:15:07 -0500 IronPort-SDR: z4g8AvilOA0RXbtLgwde2wgYosT1ChlAMCchPQA9MKvGvEViZ7A7qhK8J4FDDUZOZTHd73XSz5 nAh8GuSK95GA== X-IronPort-AV: E=McAfee;i="6000,8403,9888"; a="200751936" X-IronPort-AV: E=Sophos;i="5.81,161,1610438400"; d="scan'208";a="200751936" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2021 03:13:51 -0800 IronPort-SDR: 72BhK+PYX5SXFdE5xSaBmV/sMqYWgucbXpUuZsoL6ck754NVlfg0TKmzD9cv+oeAOc+OoAyGqy 7pJ38Q+yx+8g== X-IronPort-AV: E=Sophos;i="5.81,161,1610438400"; d="scan'208";a="374455108" Received: from anveshag-mobl1.amr.corp.intel.com (HELO intel.com) ([10.209.119.193]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2021 03:13:49 -0800 Date: Mon, 8 Feb 2021 06:13:47 -0500 From: Rodrigo Vivi To: Lyude Paul Cc: dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, David Airlie , Anshuman Gupta , Lucas De Marchi , open list , Gwan-gyeong Mun , Manasi Navare , Uma Shankar , Sean Paul , Dave Airlie Subject: Re: [RFC v3 06/10] drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight Message-ID: <20210208111347.GB4798@intel.com> References: <20210205234515.1216538-1-lyude@redhat.com> <20210205234515.1216538-7-lyude@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210205234515.1216538-7-lyude@redhat.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 05, 2021 at 06:45:10PM -0500, Lyude Paul wrote: > Since we're about to be moving this code into shared DRM helpers, we might > as well start to cache certain backlight capabilities that can be > determined from the EDP DPCD, and are likely to be relevant to the majority > of drivers using said helpers. The main purpose of this is just to prevent > every driver from having to check everything against the eDP DPCD using DP > macros, which makes the code slightly easier to read (especially since the > names of some of the eDP capabilities don't exactly match up with what we > actually need to use them for, like DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT > for instance). > > Signed-off-by: Lyude Paul Reviewed-by: Rodrigo Vivi > --- > .../drm/i915/display/intel_display_types.h | 2 ++ > .../drm/i915/display/intel_dp_aux_backlight.c | 29 ++++++++++++------- > 2 files changed, 21 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index f4b26e1dbaaf..16824eb3ef93 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -265,6 +265,8 @@ struct intel_panel { > struct { > u8 pwmgen_bit_count; > u8 pwm_freq_pre_divider; > + bool lsb_reg_used; > + bool aux_enable; > } vesa; > struct { > bool sdr_uses_aux; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > index 95e3e344cf40..f5ae2fb34c1f 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > @@ -270,13 +270,14 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi > } > > /* VESA backlight callbacks */ > -static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable) > +static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable) > { > + struct intel_dp *intel_dp = intel_attached_dp(connector); > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > u8 reg_val = 0; > > /* Early return when display use other mechanism to enable backlight. */ > - if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)) > + if (!connector->panel.backlight.edp.vesa.aux_enable) > return; > > if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) { > @@ -339,9 +340,11 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en > DP_EDP_BACKLIGHT_BRIGHTNESS_MSB); > return 0; > } > - level = read_val[0]; > - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) > + > + if (connector->panel.backlight.edp.vesa.lsb_reg_used) > level = (read_val[0] << 8 | read_val[1]); > + else > + level = read_val[0]; > > return level; > } > @@ -359,13 +362,14 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > u8 vals[2] = { 0x0 }; > > - vals[0] = level; > - > /* Write the MSB and/or LSB */ > - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) { > + if (connector->panel.backlight.edp.vesa.lsb_reg_used) { > vals[0] = (level & 0xFF00) >> 8; > vals[1] = (level & 0xFF); > + } else { > + vals[0] = level; > } > + > if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals, > sizeof(vals)) != sizeof(vals)) { > drm_dbg_kms(&i915->drm, > @@ -419,14 +423,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state, > } > > intel_dp_aux_vesa_set_backlight(conn_state, level); > - set_vesa_backlight_enable(intel_dp, true); > + set_vesa_backlight_enable(connector, true); > } > > static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state, > u32 level) > { > - set_vesa_backlight_enable(enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)), > - false); > + set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false); > } > > /* > @@ -524,8 +527,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto > static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, > enum pipe pipe) > { > + struct intel_dp *intel_dp = intel_attached_dp(connector); > struct intel_panel *panel = &connector->panel; > > + if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) > + panel->backlight.edp.vesa.aux_enable = true; > + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) > + panel->backlight.edp.vesa.lsb_reg_used = true; > + > panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector); > if (!panel->backlight.max) > return -ENODEV; > -- > 2.29.2 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel