From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-nvdimm@lists.01.org>,
<linux-pci@vger.kernel.org>, Bjorn Helgaas <helgaas@kernel.org>,
"Chris Browy" <cbrowy@avery-design.com>,
Christoph Hellwig <hch@infradead.org>,
"Dan Williams" <dan.j.williams@intel.com>,
David Hildenbrand <david@redhat.com>,
David Rientjes <rientjes@google.com>,
Ira Weiny <ira.weiny@intel.com>,
"Jon Masters" <jcm@jonmasters.org>,
Rafael Wysocki <rafael.j.wysocki@intel.com>,
Randy Dunlap <rdunlap@infradead.org>,
Vishal Verma <vishal.l.verma@intel.com>,
"John Groves (jgroves)" <jgroves@micron.com>,
"Kelley, Sean V" <sean.v.kelley@intel.com>,
Colin Ian King <colin.king@canonical.com>,
Dan Carpenter <dan.carpenter@oracle.com>
Subject: Re: [PATCH v5 2/9] cxl/mem: Find device capabilities
Date: Wed, 17 Feb 2021 12:22:53 +0000 [thread overview]
Message-ID: <20210217122253.00007bc2@Huawei.com> (raw)
In-Reply-To: <20210217040958.1354670-3-ben.widawsky@intel.com>
On Tue, 16 Feb 2021 20:09:51 -0800
Ben Widawsky <ben.widawsky@intel.com> wrote:
> Provide enough functionality to utilize the mailbox of a memory device.
> The mailbox is used to interact with the firmware running on the memory
> device. The flow is proven with one implemented command, "identify".
> Because the class code has already told the driver this is a memory
> device and the identify command is mandatory.
>
> CXL devices contain an array of capabilities that describe the
> interactions software can have with the device or firmware running on
> the device. A CXL compliant device must implement the device status and
> the mailbox capability. Additionally, a CXL compliant memory device must
> implement the memory device capability. Each of the capabilities can
> [will] provide an offset within the MMIO region for interacting with the
> CXL device.
>
> The capabilities tell the driver how to find and map the register space
> for CXL Memory Devices. The registers are required to utilize the CXL
> spec defined mailbox interface. The spec outlines two mailboxes, primary
> and secondary. The secondary mailbox is earmarked for system firmware,
> and not handled in this driver.
>
> Primary mailboxes are capable of generating an interrupt when submitting
> a background command. That implementation is saved for a later time.
>
> Reported-by: Colin Ian King <colin.king@canonical.com> (coverity)
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> (smatch)
> Link: https://www.computeexpresslink.org/download-the-specification
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com> (v2)
Looks good to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
next prev parent reply other threads:[~2021-02-17 12:24 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-17 4:09 [PATCH v5 0/9] CXL 2.0 Support Ben Widawsky
2021-02-17 4:09 ` [PATCH v5 1/9] cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints Ben Widawsky
2021-02-20 0:54 ` Konrad Rzeszutek Wilk
2021-02-17 4:09 ` [PATCH v5 2/9] cxl/mem: Find device capabilities Ben Widawsky
2021-02-17 12:22 ` Jonathan Cameron [this message]
2021-02-17 4:09 ` [PATCH v5 3/9] cxl/mem: Register CXL memX devices Ben Widawsky
2021-02-17 4:09 ` [PATCH v5 4/9] cxl/mem: Add basic IOCTL interface Ben Widawsky
2021-02-17 14:16 ` Jonathan Cameron
2021-02-20 1:22 ` Konrad Rzeszutek Wilk
2021-02-20 16:33 ` Ben Widawsky
2021-02-20 17:48 ` Dan Williams
2021-02-17 4:09 ` [PATCH v5 5/9] cxl/mem: Add a "RAW" send command Ben Widawsky
2021-02-20 1:03 ` Konrad Rzeszutek Wilk
2021-02-17 4:09 ` [PATCH v5 6/9] cxl/mem: Enable commands via CEL Ben Widawsky
2021-02-20 1:11 ` Konrad Rzeszutek Wilk
2021-02-17 4:09 ` [PATCH v5 7/9] cxl/mem: Add set of informational commands Ben Widawsky
2021-02-20 1:12 ` Konrad Rzeszutek Wilk
2021-02-17 4:09 ` [PATCH v5 8/9] MAINTAINERS: Add maintainers of the CXL driver Ben Widawsky
2021-02-17 4:09 ` [RFC PATCH v5 9/9] cxl/mem: Add payload dumping for debug Ben Widawsky
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