From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48C3AC433DB for ; Thu, 25 Feb 2021 06:39:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E34CB64EDB for ; Thu, 25 Feb 2021 06:39:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234141AbhBYGjS (ORCPT ); Thu, 25 Feb 2021 01:39:18 -0500 Received: from mga06.intel.com ([134.134.136.31]:22397 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233443AbhBYGjE (ORCPT ); Thu, 25 Feb 2021 01:39:04 -0500 IronPort-SDR: 3Jgr1/AAtrH5ZQLanh9ZOIy3GpLwuPldVK2fTHuscqAWktBfZTXTtD8EsLZjpQYU2q7qu2CeML XiShcpXG1JVg== X-IronPort-AV: E=McAfee;i="6000,8403,9905"; a="246838678" X-IronPort-AV: E=Sophos;i="5.81,205,1610438400"; d="scan'208";a="246838678" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2021 22:36:07 -0800 IronPort-SDR: b1uBW76MFmyrNqsrvdjoyuJnl1fvYGq2T20iZH3pal/7Jd65kstvAKC1sZWUNimYr+kbSlSEyJ fKY3eXKYlmgg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,205,1610438400"; d="scan'208";a="499965313" Received: from allen-box.sh.intel.com ([10.239.159.128]) by fmsmga001.fm.intel.com with ESMTP; 24 Feb 2021 22:36:02 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon Cc: ashok.raj@intel.com, kevin.tian@intel.com, jacob.jun.pan@intel.com, yi.l.liu@intel.com, sanjay.k.kumar@intel.com, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu , Jacob Pan Subject: [PATCH 4/5] iommu/vt-d: Use user privilege for RID2PASID translation Date: Thu, 25 Feb 2021 14:26:53 +0800 Message-Id: <20210225062654.2864322-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210225062654.2864322-1-baolu.lu@linux.intel.com> References: <20210225062654.2864322-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When first-level page tables are used for IOVA translation, we use user privilege by setting U/S bit in the page table entry. This is to make it consistent with the second level translation, where the U/S enforcement is not available. Clear the SRE (Supervisor Request Enable) field in the pasid table entry of RID2PASID so that requests requesting the supervisor privilege are blocked and treated as DMA remapping faults. Suggested-by: Jacob Pan Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level") Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 7 +++++-- drivers/iommu/intel/pasid.c | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index f41b184ce6eb..b14427d8121f 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2495,9 +2495,9 @@ static int domain_setup_first_level(struct intel_iommu *iommu, struct device *dev, u32 pasid) { - int flags = PASID_FLAG_SUPERVISOR_MODE; struct dma_pte *pgd = domain->pgd; int agaw, level; + int flags = 0; /* * Skip top levels of page tables for iommu which has @@ -2513,7 +2513,10 @@ static int domain_setup_first_level(struct intel_iommu *iommu, if (level != 4 && level != 5) return -EINVAL; - flags |= (level == 5) ? PASID_FLAG_FL5LP : 0; + if (pasid != PASID_RID2PASID) + flags |= PASID_FLAG_SUPERVISOR_MODE; + if (level == 5) + flags |= PASID_FLAG_FL5LP; return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid, domain->iommu_did[iommu->seq_id], diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index f26cb6195b2c..07531e5edfa2 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -647,7 +647,8 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, * Since it is a second level only translation setup, we should * set SRE bit as well (addresses are expected to be GPAs). */ - pasid_set_sre(pte); + if (pasid != PASID_RID2PASID) + pasid_set_sre(pte); pasid_set_present(pte); pasid_flush_caches(iommu, pte, pasid, did); -- 2.25.1