* [PATCH v2 1/3] dt-bindings: mtd: Convert Qcom NANDc binding to YAML
2021-02-25 4:11 [PATCH v2 0/3] Add support for secure regions in Qcom NANDc driver Manivannan Sadhasivam
@ 2021-02-25 4:11 ` Manivannan Sadhasivam
2021-02-25 4:11 ` [PATCH v2 2/3] dt-bindings: mtd: Add a property to declare secure regions in NAND chips Manivannan Sadhasivam
2021-02-25 4:11 ` [PATCH v2 3/3] mtd: rawnand: qcom: Add support for secure regions in NAND memory Manivannan Sadhasivam
2 siblings, 0 replies; 6+ messages in thread
From: Manivannan Sadhasivam @ 2021-02-25 4:11 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt
Cc: linux-arm-msm, linux-mtd, devicetree, linux-kernel,
boris.brezillon, Daniele.Palmas, bjorn.andersson,
Manivannan Sadhasivam
Convert Qcom NANDc devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../devicetree/bindings/mtd/qcom,nandc.yaml | 196 ++++++++++++++++++
.../devicetree/bindings/mtd/qcom_nandc.txt | 142 -------------
2 files changed, 196 insertions(+), 142 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
delete mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
new file mode 100644
index 000000000000..84ad7ff30121
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm NAND controller
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq806x-nand
+ - qcom,ipq4019-nand
+ - qcom,ipq6018-nand
+ - qcom,ipq8074-nand
+ - qcom,sdx55-nand
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Core Clock
+ - description: Always ON Clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: aon
+
+ "#address-cells": true
+ "#size-cells": true
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ nand-bus-width:
+ const: 8
+
+ nand-ecc-strength:
+ enum: [1, 4, 8]
+
+ nand-ecc-step-size:
+ enum:
+ - 512
+
+allOf:
+ - $ref: "nand-controller.yaml#"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,ipq806x-nand
+ then:
+ properties:
+ dmas:
+ items:
+ - description: rxtx DMA channel
+
+ dma-names:
+ items:
+ - const: rxtx
+
+ qcom,cmd-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain the ADM command type CRCI block instance number
+ specified for the NAND controller on the given platform
+
+ qcom,data-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain the ADM data type CRCI block instance number
+ specified for the NAND controller on the given platform
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq4019-nand
+ - qcom,ipq6018-nand
+ - qcom,ipq8074-nand
+ - qcom,sdx55-nand
+
+ then:
+ properties:
+ dmas:
+ items:
+ - description: tx DMA channel
+ - description: rx DMA channel
+ - description: cmd DMA channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+ - const: cmd
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+ nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+ };
+
+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+ nand-controller@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
deleted file mode 100644
index 5647913d8837..000000000000
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ /dev/null
@@ -1,142 +0,0 @@
-* Qualcomm NAND controller
-
-Required properties:
-- compatible: must be one of the following:
- * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
- SoC and it uses ADM DMA
- * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
- IPQ4019 SoC and it uses BAM DMA
- * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
- IPQ6018 SoC and it uses BAM DMA
- * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
- IPQ8074 SoC and it uses BAM DMA
- * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
- SDX55 SoC and it uses BAM DMA
-
-- reg: MMIO address range
-- clocks: must contain core clock and always on clock
-- clock-names: must contain "core" for the core clock and "aon" for the
- always on clock
-
-EBI2 specific properties:
-- dmas: DMA specifier, consisting of a phandle to the ADM DMA
- controller node and the channel number to be used for
- NAND. Refer to dma.txt and qcom_adm.txt for more details
-- dma-names: must be "rxtx"
-- qcom,cmd-crci: must contain the ADM command type CRCI block instance
- number specified for the NAND controller on the given
- platform
-- qcom,data-crci: must contain the ADM data type CRCI block instance
- number specified for the NAND controller on the given
- platform
-
-QPIC specific properties:
-- dmas: DMA specifier, consisting of a phandle to the BAM DMA
- and the channel number to be used for NAND. Refer to
- dma.txt, qcom_bam_dma.txt for more details
-- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
-- #address-cells: <1> - subnodes give the chip-select number
-- #size-cells: <0>
-
-* NAND chip-select
-
-Each controller may contain one or more subnodes to represent enabled
-chip-selects which (may) contain NAND flash chips. Their properties are as
-follows.
-
-Required properties:
-- reg: a single integer representing the chip-select
- number (e.g., 0, 1, 2, etc.)
-- #address-cells: see partition.txt
-- #size-cells: see partition.txt
-
-Optional properties:
-- nand-bus-width: see nand-controller.yaml
-- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
- be used according to chip requirement and available
- OOB size.
-
-Each nandcs device node may optionally contain a 'partitions' sub-node, which
-further contains sub-nodes describing the flash partition mapping. See
-partition.txt for more detail.
-
-Example:
-
-nand-controller@1ac00000 {
- compatible = "qcom,ipq806x-nand";
- reg = <0x1ac00000 0x800>;
-
- clocks = <&gcc EBI2_CLK>,
- <&gcc EBI2_AON_CLK>;
- clock-names = "core", "aon";
-
- dmas = <&adm_dma 3>;
- dma-names = "rxtx";
- qcom,cmd-crci = <15>;
- qcom,data-crci = <3>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- nand@0 {
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "boot-nand";
- reg = <0 0x58a0000>;
- };
-
- partition@58a0000 {
- label = "fs-nand";
- reg = <0x58a0000 0x4000000>;
- };
- };
- };
-};
-
-nand-controller@79b0000 {
- compatible = "qcom,ipq4019-nand";
- reg = <0x79b0000 0x1000>;
-
- clocks = <&gcc GCC_QPIC_CLK>,
- <&gcc GCC_QPIC_AHB_CLK>;
- clock-names = "core", "aon";
-
- dmas = <&qpicbam 0>,
- <&qpicbam 1>,
- <&qpicbam 2>;
- dma-names = "tx", "rx", "cmd";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- nand@0 {
- reg = <0>;
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "boot-nand";
- reg = <0 0x58a0000>;
- };
-
- partition@58a0000 {
- label = "fs-nand";
- reg = <0x58a0000 0x4000000>;
- };
- };
- };
-};
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/3] mtd: rawnand: qcom: Add support for secure regions in NAND memory
2021-02-25 4:11 [PATCH v2 0/3] Add support for secure regions in Qcom NANDc driver Manivannan Sadhasivam
2021-02-25 4:11 ` [PATCH v2 1/3] dt-bindings: mtd: Convert Qcom NANDc binding to YAML Manivannan Sadhasivam
2021-02-25 4:11 ` [PATCH v2 2/3] dt-bindings: mtd: Add a property to declare secure regions in NAND chips Manivannan Sadhasivam
@ 2021-02-25 4:11 ` Manivannan Sadhasivam
2021-02-25 7:47 ` Miquel Raynal
2 siblings, 1 reply; 6+ messages in thread
From: Manivannan Sadhasivam @ 2021-02-25 4:11 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt
Cc: linux-arm-msm, linux-mtd, devicetree, linux-kernel,
boris.brezillon, Daniele.Palmas, bjorn.andersson,
Manivannan Sadhasivam
On a typical end product, a vendor may choose to secure some regions in
the NAND memory which are supposed to stay intact between FW upgrades.
The access to those regions will be blocked by a secure element like
Trustzone. So the normal world software like Linux kernel should not
touch these regions (including reading).
The regions are declared using a NAND chip DT property,
"nand-secure-regions". So let's make use of this property and skip
access to the secure regions present in a system.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/mtd/nand/raw/qcom_nandc.c | 72 +++++++++++++++++++++++++++----
1 file changed, 63 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index fd4c318b520f..aa4ca298d357 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -431,6 +431,11 @@ struct qcom_nand_controller {
* @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
* ecc/non-ecc mode for the current nand flash
* device
+ *
+ * @sec_regions: Array representing the secure regions in the
+ * NAND chip
+ *
+ * @nr_sec_regions: Number of secure regions in the NAND chip
*/
struct qcom_nand_host {
struct nand_chip chip;
@@ -453,6 +458,9 @@ struct qcom_nand_host {
u32 ecc_bch_cfg;
u32 clrflashstatus;
u32 clrreadstatus;
+
+ u32 *sec_regions;
+ u8 nr_sec_regions;
};
/*
@@ -662,16 +670,27 @@ static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset,
}
/* helper to configure address register values */
-static void set_address(struct qcom_nand_host *host, u16 column, int page)
+static int set_address(struct qcom_nand_host *host, u16 column, int page)
{
struct nand_chip *chip = &host->chip;
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+ u32 offs = page << chip->page_shift;
+ int i, j;
+
+ /* Skip touching the secure regions if present */
+ for (i = 0, j = 0; i < host->nr_sec_regions; i++, j += 2) {
+ if (offs >= host->sec_regions[j] &&
+ (offs <= host->sec_regions[j] + host->sec_regions[j + 1]))
+ return -EIO;
+ }
if (chip->options & NAND_BUSWIDTH_16)
column >>= 1;
nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column);
nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff);
+
+ return 0;
}
/*
@@ -1491,13 +1510,13 @@ static void qcom_nandc_command(struct nand_chip *chip, unsigned int command,
WARN_ON(column != 0);
host->use_ecc = true;
- set_address(host, 0, page_addr);
+ ret = set_address(host, 0, page_addr);
update_rw_regs(host, ecc->steps, true);
break;
case NAND_CMD_SEQIN:
WARN_ON(column != 0);
- set_address(host, 0, page_addr);
+ ret = set_address(host, 0, page_addr);
break;
case NAND_CMD_PAGEPROG:
@@ -1615,7 +1634,10 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
host->use_ecc = false;
clear_bam_transaction(nandc);
- set_address(host, host->cw_size * cw, page);
+ ret = set_address(host, host->cw_size * cw, page);
+ if (ret)
+ return ret;
+
update_rw_regs(host, 1, true);
config_nand_page_read(nandc);
@@ -1943,7 +1965,10 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
/* prepare a clean read buffer */
memset(nandc->data_buffer, 0xff, size);
- set_address(host, host->cw_size * (ecc->steps - 1), page);
+ ret = set_address(host, host->cw_size * (ecc->steps - 1), page);
+ if (ret)
+ return ret;
+
update_rw_regs(host, 1, true);
config_nand_single_cw_page_read(nandc, host->use_ecc);
@@ -2005,12 +2030,16 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page)
struct qcom_nand_host *host = to_qcom_nand_host(chip);
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
+ int ret;
clear_read_regs(nandc);
clear_bam_transaction(nandc);
host->use_ecc = true;
- set_address(host, 0, page);
+ ret = set_address(host, 0, page);
+ if (ret)
+ return ret;
+
update_rw_regs(host, ecc->steps, true);
return read_page_ecc(host, NULL, chip->oob_poi, page);
@@ -2188,7 +2217,10 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page)
mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob,
0, mtd->oobavail);
- set_address(host, host->cw_size * (ecc->steps - 1), page);
+ ret = set_address(host, host->cw_size * (ecc->steps - 1), page);
+ if (ret)
+ return ret;
+
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
@@ -2267,7 +2299,10 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs)
/* prepare write */
host->use_ecc = false;
- set_address(host, host->cw_size * (ecc->steps - 1), page);
+ ret = set_address(host, host->cw_size * (ecc->steps - 1), page);
+ if (ret)
+ return ret;
+
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
@@ -2830,7 +2865,8 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
struct nand_chip *chip = &host->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
struct device *dev = nandc->dev;
- int ret;
+ struct property *prop;
+ int ret, length, nr_elem;
ret = of_property_read_u32(dn, "reg", &host->cs);
if (ret) {
@@ -2886,6 +2922,24 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
}
}
+ /*
+ * Look for secure regions in the NAND chip. These regions are supposed
+ * to be protected by a secure element like Trustzone. So the read/write
+ * accesses to these regions will be blocked in the runtime by this
+ * driver.
+ */
+ prop = of_find_property(dn, "nand-secure-regions", &length);
+ if (prop) {
+ nr_elem = length / sizeof(u32);
+ host->nr_sec_regions = nr_elem / 2;
+
+ host->sec_regions = devm_kcalloc(dev, nr_elem, sizeof(u32), GFP_KERNEL);
+ if (!host->sec_regions)
+ return -ENOMEM;
+
+ of_property_read_u32_array(dn, "nand-secure-regions", host->sec_regions, nr_elem);
+ }
+
ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0);
if (ret)
nand_cleanup(chip);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread