From: Lee Jones <lee.jones@linaro.org>
To: Xu Yilun <yilun.xu@intel.com>
Cc: linux-kernel@vger.kernel.org, trix@redhat.com,
matthew.gerlach@linux.intel.com, russell.h.weight@intel.com,
lgoncalv@redhat.com, hao.wu@intel.com
Subject: Re: [PATCH v3 2/4] mfd: intel-m10-bmc: Simplify the legacy version reg definition
Date: Wed, 10 Mar 2021 09:16:25 +0000 [thread overview]
Message-ID: <20210310091625.GJ4931@dell> (raw)
In-Reply-To: <1614578385-26955-3-git-send-email-yilun.xu@intel.com>
On Mon, 01 Mar 2021, Xu Yilun wrote:
> The version register is the only one in the legacy I/O space to be
> accessed, so it is not necessary to define the legacy base & version
> register offset. A direct definition of the legacy version register
> address would be fine.
>
> Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> Reviewed-by: Tom Rix <trix@redhat.com>
> ---
> v3: no change, rebased to 5.12-rc1
> ---
> drivers/mfd/intel-m10-bmc.c | 12 +++++-------
> include/linux/mfd/intel-m10-bmc.h | 2 +-
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
> index 06c9775..0d2c03f 100644
> --- a/drivers/mfd/intel-m10-bmc.c
> +++ b/drivers/mfd/intel-m10-bmc.c
> @@ -117,16 +117,14 @@ static int check_m10bmc_version(struct intel_m10bmc *ddata)
>
> /*
> * This check is to filter out the very old legacy BMC versions,
> - * M10BMC_LEGACY_SYS_BASE is the offset to this old block of mmio
> - * registers. In the old BMC chips, the BMC version info is stored
> - * in this old version register (M10BMC_LEGACY_SYS_BASE +
> - * M10BMC_BUILD_VER), so its read out value would have not been
> - * LEGACY_INVALID (0xffffffff). But in new BMC chips that the
> + * 0x300400 is the offset to this old block of mmio registers. In the
Not sure we want actual addresses in comments.
Please reword this to cover just the latest solution.
> + * old BMC chips, the BMC version info is stored in this old version
> + * register (0x300400 + 0x68), so its read out value would have not
> + * been LEGACY_INVALID (0xffffffff). But in new BMC chips that the
> * driver supports, the value of this register should be
> * LEGACY_INVALID.
> */
> - ret = m10bmc_raw_read(ddata,
> - M10BMC_LEGACY_SYS_BASE + M10BMC_BUILD_VER, &v);
> + ret = m10bmc_raw_read(ddata, M10BMC_LEGACY_BUILD_VER, &v);
> if (ret)
> return -ENODEV;
>
> diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h
> index 9b54ca1..4f1071f 100644
> --- a/include/linux/mfd/intel-m10-bmc.h
> +++ b/include/linux/mfd/intel-m10-bmc.h
> @@ -9,7 +9,7 @@
>
> #include <linux/regmap.h>
>
> -#define M10BMC_LEGACY_SYS_BASE 0x300400
> +#define M10BMC_LEGACY_BUILD_VER 0x300468
> #define M10BMC_SYS_BASE 0x300800
> #define M10BMC_MEM_END 0x1fffffff
>
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
next prev parent reply other threads:[~2021-03-10 9:17 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-01 5:59 [PATCH v3 0/4] Some improvement for Intel MAX 10 MFD drivers Xu Yilun
2021-03-01 5:59 ` [PATCH v3 1/4] mfd: intel-m10-bmc: Fix the register access range Xu Yilun
2021-03-10 9:16 ` Lee Jones
2021-03-01 5:59 ` [PATCH v3 2/4] mfd: intel-m10-bmc: Simplify the legacy version reg definition Xu Yilun
2021-03-10 9:16 ` Lee Jones [this message]
2021-03-10 15:53 ` Xu Yilun
2021-03-01 5:59 ` [PATCH v3 3/4] mfd: intel-m10-bmc: Add access table configuration to the regmap Xu Yilun
2021-03-10 9:18 ` Lee Jones
2021-03-01 5:59 ` [PATCH v3 4/4] MAINTAINERS: Add entry for Intel MAX 10 mfd driver Xu Yilun
2021-03-10 9:19 ` Lee Jones
2021-03-08 2:04 ` [PATCH v3 0/4] Some improvement for Intel MAX 10 MFD drivers Xu Yilun
2021-03-08 9:01 ` Lee Jones
2021-03-08 14:42 ` Xu Yilun
2021-03-08 15:31 ` Lee Jones
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