From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Swapnil Jakhade <sjakhade@cadence.com>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Lokesh Vutla <lokeshvutla@ti.com>
Subject: [PATCH v6 13/13] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
Date: Wed, 10 Mar 2021 21:15:58 +0530 [thread overview]
Message-ID: <20210310154558.32078-14-kishon@ti.com> (raw)
In-Reply-To: <20210310154558.32078-1-kishon@ti.com>
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 40 ++++++++++++++++++++++--
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 039ca10db59d..5c68e31c5939 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -768,6 +768,40 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
+{
+ int ret;
+
+ ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
+ if (ret)
+ goto err_pll_cmnlc;
+
+ ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
+ if (ret)
+ goto err_pll_cmnlc1;
+
+ return 0;
+
+err_pll_cmnlc1:
+ clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
+
+err_pll_cmnlc:
+ clk_disable_unprepare(sp->input_clks[PHY_CLK]);
+
+ return ret;
+}
+
+static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
+{
+ clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]);
+ clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]);
+ clk_disable_unprepare(sp->input_clks[PHY_CLK]);
+}
+
static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
struct device *dev)
{
@@ -848,7 +882,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
if (ret)
goto unregister_clk;
- ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
+ ret = cdns_sierra_phy_enable_clocks(sp);
if (ret)
goto unregister_clk;
@@ -925,7 +959,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
reset_control_put(sp->phys[i].lnk_rst);
of_node_put(child);
clk_disable:
- clk_disable_unprepare(sp->input_clks[PHY_CLK]);
+ cdns_sierra_phy_disable_clocks(sp);
reset_control_assert(sp->apb_rst);
unregister_clk:
cdns_sierra_clk_unregister(sp);
@@ -941,6 +975,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev)
reset_control_assert(phy->apb_rst);
pm_runtime_disable(&pdev->dev);
+ cdns_sierra_phy_disable_clocks(phy);
/*
* The device level resets will be put automatically.
* Need to put the subnode resets here though.
@@ -950,7 +985,6 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev)
reset_control_put(phy->phys[i].lnk_rst);
}
- clk_disable_unprepare(phy->input_clks[PHY_CLK]);
cdns_sierra_clk_unregister(phy);
return 0;
--
2.17.1
next prev parent reply other threads:[~2021-03-10 15:47 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 15:45 [PATCH v6 00/13] PHY: Add support in Sierra to use external clock Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 01/13] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 02/13] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Kishon Vijay Abraham I
2021-03-15 5:47 ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 03/13] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Kishon Vijay Abraham I
2021-03-15 5:50 ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 04/13] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 05/13] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Kishon Vijay Abraham I
2021-03-15 5:50 ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 06/13] phy: cadence: cadence-sierra: Move all reset_control_get*() " Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 07/13] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 08/13] phy: cadence-torrent: Use a common header file for Cadence SERDES Kishon Vijay Abraham I
2021-03-15 5:51 ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 09/13] phy: cadence: cadence-sierra: Add array of input clocks in "struct cdns_sierra_phy" Kishon Vijay Abraham I
2021-03-15 5:52 ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` [PATCH v6 10/13] phy: cadence: cadence-sierra: Add missing clk_disable_unprepare() in .remove callback Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 11/13] dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider Kishon Vijay Abraham I
2021-03-10 15:45 ` [PATCH v6 12/13] phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Kishon Vijay Abraham I
2021-03-15 6:15 ` Swapnil Kashinath Jakhade
2021-03-10 15:45 ` Kishon Vijay Abraham I [this message]
2021-03-15 5:54 ` [PATCH v6 13/13] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Swapnil Kashinath Jakhade
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