From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2208AC433E9 for ; Sun, 14 Mar 2021 16:01:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EE0B864EC6 for ; Sun, 14 Mar 2021 16:01:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234455AbhCNQBW (ORCPT ); Sun, 14 Mar 2021 12:01:22 -0400 Received: from mga14.intel.com ([192.55.52.115]:7144 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234055AbhCNQAe (ORCPT ); Sun, 14 Mar 2021 12:00:34 -0400 IronPort-SDR: e9OoYv1lSk68Q4SFXlo0XYEV5XkcaCgZ32zSwx2Z5MrFMlXHOBwvT4FMWFocWQovO2by5iKTe7 pG4IZmVfNUCQ== X-IronPort-AV: E=McAfee;i="6000,8403,9923"; a="188360700" X-IronPort-AV: E=Sophos;i="5.81,248,1610438400"; d="scan'208";a="188360700" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2021 09:00:34 -0700 IronPort-SDR: TzFY1PShlwmlYWWb27cNqY1xn9i//P14d4JXGr+6/iIw9So1MgzD+45QG+5PuSBWS1cUdFKQbu QpYebQC5X2kw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,248,1610438400"; d="scan'208";a="439530637" Received: from clx-ap-likexu.sh.intel.com ([10.239.48.108]) by FMSMGA003.fm.intel.com with ESMTP; 14 Mar 2021 09:00:31 -0700 From: Like Xu To: Paolo Bonzini , Sean Christopherson Cc: Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, x86@kernel.org, wei.w.wang@intel.com, linux-kernel@vger.kernel.org, Like Xu , Kan Liang , Peter Zijlstra , Borislav Petkov , Ingo Molnar , Andi Kleen Subject: [PATCH v4 03/11] perf/x86/lbr: Skip checking for the existence of LBR_TOS for Arch LBR Date: Sun, 14 Mar 2021 23:52:16 +0800 Message-Id: <20210314155225.206661-4-like.xu@linux.intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210314155225.206661-1-like.xu@linux.intel.com> References: <20210314155225.206661-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Architecture LBR does not have MSR_LBR_TOS (0x000001c9). KVM will generate #GP for this MSR access, thereby preventing the initialization of the guest LBR. Cc: Kan Liang Cc: Peter Zijlstra Cc: Borislav Petkov Cc: Ingo Molnar Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR") Signed-off-by: Like Xu Reviewed-by: Kan Liang Reviewed-by: Andi Kleen --- arch/x86/events/intel/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 7bb96ac87615..0338e354826d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5568,7 +5568,8 @@ __init int intel_pmu_init(void) * Check all LBR MSR here. * Disable LBR access if any LBR MSRs can not be accessed. */ - if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) + if (x86_pmu.lbr_nr && !boot_cpu_has(X86_FEATURE_ARCH_LBR) && + !check_msr(x86_pmu.lbr_tos, 0x3UL)) x86_pmu.lbr_nr = 0; for (i = 0; i < x86_pmu.lbr_nr; i++) { if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && -- 2.29.2