Re: [PATCH v3 4/4] clk: bcm: Add BCM63268 timer clock and reset driver

Florian Fainelli
2023-03-21T23:10:11Z

On 3/21/23 16:06, Stephen Boyd wrote:
> Quoting Florian Fainelli (2023-03-21 16:00:29)
>> On 3/21/23 15:57, Stephen Boyd wrote:
>>> Quoting Álvaro Fernández Rojas (2023-03-21 13:10:22)
>>>> diff --git a/drivers/clk/bcm/clk-bcm63268-timer.c b/drivers/clk/bcm/clk-bcm63268-timer.c
>>>> new file mode 100644
>>>> index 000000000000..6a1fdd193cb5
>>>> --- /dev/null
>>>> +++ b/drivers/clk/bcm/clk-bcm63268-timer.c
>>>> @@ -0,0 +1,232 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * BCM63268 Timer Clock and Reset Controller Driver
>>> [...]
>>>> +
>>>> +static inline struct bcm63268_tclkrst_hw *
>>>> +to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
>>>> +{
>>>> + return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
>>>> +}
>>>> +
>>>> +static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
>>>> + unsigned long id, bool assert)
>>>> +{
>>>> + struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
>>>> + unsigned long flags;
>>>> + uint32_t val;
>>>> +
>>>> + spin_lock_irqsave(&reset->lock, flags);
>>>> + val = __raw_readl(reset->regs);
>>>
>>> Use regular ol readl() here, unless you have some need for no barrires
>>> or byte swapping.
>>
>> These SoCs are big-endian, require native endian register access and
>> have no posted writes within their bus logic (UBUS) and require no
>> barriers, hence the use of __raw_readl() and __raw_writel() is adequate.
>>
>
> Use ioread32be() then?

BCM63xx drivers tend to use __raw_{read,write}l for consistency and to
make it clear that no barriers, no endian swapping is necessary, I would
prefer to remain consistent with that convention.
--
Florian