Re: [PATCH 3/5] arm: dts: qcom: Add support for MSM8226 SoC

Stephen Boyd
2021-03-26T18:21:56Z

Quoting Bartosz Dudziak (2021-03-26 07:58:14)
> This patch adds basic device tree support for MSM8226 SoC which belongs

git grep "This patch" -- Documentation/process/submitting-patches.rst

> to the Snapdragon 400 family. For now, this file adds the basic nodes
> like gcc, pinctrl and other required configuration for booting up to
> the serial console.
>
> Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
> ---
> arch/arm/boot/dts/qcom-msm8226.dtsi | 152 ++++++++++++++++++++++++++++
> 1 file changed, 152 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi
>
> diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
> new file mode 100644
> index 0000000000..81bb19398e
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8974.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + model = "Qualcomm Technologies, Inc. MSM8226";
> + compatible = "qcom,msm8226";
> + interrupt-parent = <&intc>;
> +
> + chosen { };
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0x0>;
> + };
> +
> + soc: soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "simple-bus";
> +
> + intc: interrupt-controller@f9000000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0xF9000000 0x1000>,

lowercase hex please.

> + <0xF9002000 0x1000>;
> + };
> +
> + gcc: clock-controller@fc400000 {
> + compatible = "qcom,gcc-msm8226";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + reg = <0xfc400000 0x4000>;
> + };
> +
> + msmgpio: pinctrl@fd510000 {
> + compatible = "qcom,msm8226-pinctrl";
> + reg = <0xfd510000 0x4000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&msmgpio 0 0 117>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + blsp1_uart3: serial@f991f000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0xf991f000 0x1000>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + restart@fc4ab000 {
> + compatible = "qcom,pshold";
> + reg = <0xfc4ab000 0x4>;
> + };
> +
> + rng@f9bff000 {
> + compatible = "qcom,prng";
> + reg = <0xf9bff000 0x200>;
> + clocks = <&gcc GCC_PRNG_AHB_CLK>;
> + clock-names = "core";
> + };
> +
> + timer@f9020000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0xf9020000 0x1000>;
> + clock-frequency = <19200000>;

Can you remove this clock-frequency property? Hopefully the firmware is
setting this frequency properly so the driver can read it out of the
registers instead of DT.

> +
> + frame@f9021000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9021000 0x1000>,
> + <0xf9022000 0x1000>;
> + };
> +
> + frame@f9023000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9023000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9024000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9024000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9025000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9025000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9026000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9026000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9027000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9027000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@f9028000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9028000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 2
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;

Same frequency comment.

> + };
> +};