From: Borislav Petkov <bp@alien8.de>
To: kan.liang@linux.intel.com
Cc: peterz@infradead.org, mingo@kernel.org,
linux-kernel@vger.kernel.org, acme@kernel.org,
tglx@linutronix.de, namhyung@kernel.org, jolsa@redhat.com,
ak@linux.intel.com, yao.jin@linux.intel.com,
alexander.shishkin@linux.intel.com, adrian.hunter@intel.com,
Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
"Ravi V. Shankar" <ravi.v.shankar@intel.com>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Subject: Re: [PATCH V4 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit
Date: Fri, 2 Apr 2021 11:24:27 +0200 [thread overview]
Message-ID: <20210402092427.GA28499@zn.tnic> (raw)
In-Reply-To: <1617322252-154215-2-git-send-email-kan.liang@linux.intel.com>
On Thu, Apr 01, 2021 at 05:10:28PM -0700, kan.liang@linux.intel.com wrote:
> From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
>
> Add feature enumeration to identify a processor with Intel Hybrid
> Technology: one in which CPUs of more than one type are the same package.
> On a hybrid processor, all CPUs support the same homogeneous (i.e.,
> symmetric) instruction set. All CPUs enumerate the same features in CPUID.
> Thus, software (user space and kernel) can run and migrate to any CPU in
> the system as well as utilize any of the enumerated features without any
> change or special provisions. The main difference among CPUs in a hybrid
> processor are power and performance properties.
>
> Cc: Andi Kleen <ak@linux.intel.com>
> Cc: Kan Liang <kan.liang@linux.intel.com>
> Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org>
> Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
> Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> Cc: linux-kernel@vger.kernel.org
> Reviewed-by: Len Brown <len.brown@intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
> ---
> Changes since v3 (as part of patchset for perf change for Alderlake)
> * None
>
> Changes since V2 (as part of patchset for perf change for Alderlake)
> * Don't show "hybrid_cpu" in /proc/cpuinfo (Boris)
>
> Changes since v1 (as part of patchset for perf change for Alderlake)
> * None
>
> Changes since v1 (in a separate posting):
> * Reworded commit message to clearly state what is Intel Hybrid
> Technology. Stress that all CPUs can run the same instruction
> set and support the same features.
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index cc96e26d69f7..1ba4a6e1690c 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -374,6 +374,7 @@
> #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
> #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
> #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */
> +#define X86_FEATURE_HYBRID_CPU (18*32+15) /* "" This part has CPUs of more than one type */
> #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
> #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
> #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
> --
Acked-by: Borislav Petkov <bp@suse.de>
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2021-04-02 9:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-02 0:10 [PATCH V4 00/25] Add Alder Lake support for perf (kernel) kan.liang
2021-04-02 0:10 ` [PATCH V4 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang
2021-04-02 9:24 ` Borislav Petkov [this message]
2021-04-02 0:10 ` [PATCH V4 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU kan.liang
2021-04-02 9:26 ` Borislav Petkov
2021-04-02 0:10 ` [PATCH V4 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang
2021-04-02 0:10 ` [PATCH V4 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang
2021-04-02 0:10 ` [PATCH V4 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang
2021-04-02 0:10 ` [PATCH V4 06/25] perf/x86: Hybrid PMU support for counters kan.liang
2021-04-02 0:10 ` [PATCH V4 07/25] perf/x86: Hybrid PMU support for unconstrained kan.liang
2021-04-02 0:10 ` [PATCH V4 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang
2021-04-02 0:10 ` [PATCH V4 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang
2021-04-02 0:10 ` [PATCH V4 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang
2021-04-02 0:10 ` [PATCH V4 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang
2021-04-02 0:10 ` [PATCH V4 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang
2021-04-02 0:10 ` [PATCH V4 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang
2021-04-02 0:10 ` [PATCH V4 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang
2021-04-02 0:10 ` [PATCH V4 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang
2021-04-02 0:10 ` [PATCH V4 16/25] perf/x86: Register hybrid PMUs kan.liang
2021-04-02 0:10 ` [PATCH V4 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang
2021-04-02 0:10 ` [PATCH V4 18/25] perf/x86/intel: Add attr_update for " kan.liang
2021-04-02 0:10 ` [PATCH V4 19/25] perf/x86: Support filter_match callback kan.liang
2021-04-02 0:10 ` [PATCH V4 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang
2021-04-02 0:10 ` [PATCH V4 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU kan.liang
2021-04-02 0:10 ` [PATCH V4 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang
2021-04-02 0:10 ` [PATCH V4 23/25] perf/x86/msr: Add Alder Lake CPU support kan.liang
2021-04-02 0:10 ` [PATCH V4 24/25] perf/x86/cstate: " kan.liang
2021-04-02 0:10 ` [PATCH V4 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang
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