From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F029DC43470 for ; Mon, 5 Apr 2021 16:04:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D05FC613D6 for ; Mon, 5 Apr 2021 16:04:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242125AbhDEQEu (ORCPT ); Mon, 5 Apr 2021 12:04:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:55648 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242012AbhDEQEY (ORCPT ); Mon, 5 Apr 2021 12:04:24 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6C5AB613C4; Mon, 5 Apr 2021 16:04:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1617638658; bh=RFmTCisCouuXXU+MSA22iqN8drWIn2LSu7R4jTz3UCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fWn3rWrT/EI72H0VKCb1cbnq+Q//ih1vypYVPhPX9OpJGdwCoY8GIm9DZ0apR4tKU +8sBg+s/Hs+WXNnh3LoG3GDjtHPji3qC3Ppus2ZrK9mL3HTmnEUbjYrIqU9ETIe8R3 UraDMecJYMOjFZ5u2crc3kdtWUHobWkX4sIGvqGryYt/+KDktuaGuFsGb8ytu10FN4 JrUH74manfJvnXKARbMF6Mek7mowwtPEDDW8n+OYN5v1/vZ4vzOP0m8qao16ia8Jub 70Gt2mSlOjoYGRpkPmytEck+DCvyAjThDOPCYC1I7VWnGk3BCdF3SQdcJJaXn8tsd5 lXwwbPwx/aXdA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Dmitry Osipenko , Thierry Reding , Sasha Levin , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH AUTOSEL 5.11 10/22] drm/tegra: dc: Don't set PLL clock to 0Hz Date: Mon, 5 Apr 2021 12:03:53 -0400 Message-Id: <20210405160406.268132-10-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210405160406.268132-1-sashal@kernel.org> References: <20210405160406.268132-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko [ Upstream commit f8fb97c915954fc6de6513cdf277103b5c6df7b3 ] RGB output doesn't allow to change parent clock rate of the display and PCLK rate is set to 0Hz in this case. The tegra_dc_commit_state() shall not set the display clock to 0Hz since this change propagates to the parent clock. The DISP clock is defined as a NODIV clock by the tegra-clk driver and all NODIV clocks use the CLK_SET_RATE_PARENT flag. This bug stayed unnoticed because by default PLLP is used as the parent clock for the display controller and PLLP silently skips the erroneous 0Hz rate changes because it always has active child clocks that don't permit rate changes. The PLLP isn't acceptable for some devices that we want to upstream (like Samsung Galaxy Tab and ASUS TF700T) due to a display panel clock rate requirements that can't be fulfilled by using PLLP and then the bug pops up in this case since parent clock is set to 0Hz, killing the display output. Don't touch DC clock if pclk=0 in order to fix the problem. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/gpu/drm/tegra/dc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 0ae3a025efe9..24362533e14c 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1688,6 +1688,11 @@ static void tegra_dc_commit_state(struct tegra_dc *dc, dev_err(dc->dev, "failed to set clock rate to %lu Hz\n", state->pclk); + + err = clk_set_rate(dc->clk, state->pclk); + if (err < 0) + dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", + dc->clk, state->pclk, err); } DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), @@ -1698,11 +1703,6 @@ static void tegra_dc_commit_state(struct tegra_dc *dc, value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); } - - err = clk_set_rate(dc->clk, state->pclk); - if (err < 0) - dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", - dc->clk, state->pclk, err); } static void tegra_dc_stop(struct tegra_dc *dc) -- 2.30.2