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[2a01:cb00:8bd:2700:41a0:a0f4:308e:afc0]) by smtp.gmail.com with ESMTPSA id l14sm17173952wrm.77.2021.04.07.14.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 14:21:29 -0700 (PDT) From: Adrien Grassein Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Anson.Huang@nxp.com, krzk@kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, qiangqing.zhang@nxp.com, alice.guo@nxp.com, aford173@gmail.com, agx@sigxcpu.org, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Adrien Grassein Subject: [PATCH v1 3/7] soc: imx: gpcv2: allow domains without power sequence control Date: Wed, 7 Apr 2021 23:21:18 +0200 Message-Id: <20210407212122.626137-4-adrien.grassein@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407212122.626137-1-adrien.grassein@gmail.com> References: <20210407212122.626137-1-adrien.grassein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On new SOCs, some domains does not have power sequence control registers. Signed-off-by: Adrien Grassein --- drivers/soc/imx/gpcv2.c | 134 +++++++++++++++++++++------------------- 1 file changed, 72 insertions(+), 62 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 7afb81489f21..d97a53502753 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -162,40 +162,44 @@ static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd) } /* Map the domain to the A53 core */ - ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, domain->bits.map); - if (ret) { - dev_err(domain->dev, "failed to map GPC PGC domain\n"); - goto disable_clocks; + if (domain->bits.map) { + ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); + if (ret) { + dev_err(domain->dev, "failed to map GPC PGC domain\n"); + goto disable_clocks; + } } /* Request Power Up of the domain */ - ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, - domain->bits.pxx, domain->bits.pxx); - if (ret) { - dev_err(domain->dev, "failed to command PGC\n"); - goto unmap; - } + if (domain->bits.pxx) { + ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + domain->bits.pxx, domain->bits.pxx); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto unmap; + } - /* - * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait - * for PUP_REQ/PDN_REQ bit to be cleared - */ - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, - value, - !(value & domain->bits.pxx), - 0, USEC_PER_MSEC); - if (ret) { - dev_err(domain->dev, "failed to command PGC\n"); - goto unmap; - } + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + value, + !(value & domain->bits.pxx), + 0, USEC_PER_MSEC); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto unmap; + } - /* Disable power control */ - ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, 0); - if (ret) { - dev_err(domain->dev, "Failed to disable power control !\n"); - goto unmap; + /* Disable power control */ + ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, 0); + if (ret) { + dev_err(domain->dev, "Failed to disable power control !\n"); + goto unmap; + } } /* request the ADB400 to power up */ @@ -212,8 +216,9 @@ static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd) genpd->name); } - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, 0); + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); /* Disable all clocks */ for (i = 0; i < domain->num_clks; i++) @@ -256,11 +261,13 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd) } /* Map the domain to the A53 core */ - ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, domain->bits.map); - if (ret) { - dev_err(domain->dev, "failed to map GPC PGC domain\n"); - goto disable_clocks; + if (domain->bits.map) { + ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); + if (ret) { + dev_err(domain->dev, "failed to map GPC PGC domain\n"); + goto disable_clocks; + } } /* request the ADB400 to power down */ @@ -278,32 +285,34 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd) } - /* Enable power control */ - ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); - if (ret) { - dev_err(domain->dev, "Failed to enable power control !\n"); - goto unmap; - } + if (domain->bits.pxx) { + /* Enable power control */ + ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + if (ret) { + dev_err(domain->dev, "Failed to enable power control !\n"); + goto unmap; + } - /* Request Power Down of the domain */ - ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, - domain->bits.pxx, domain->bits.pxx); - if (ret) { - dev_err(domain->dev, "failed to command PGC\n"); - goto unmap; - } + /* Request Power Down of the domain */ + ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + domain->bits.pxx, domain->bits.pxx); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto unmap; + } - /* - * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait - * for PUP_REQ/PDN_REQ bit to be cleared - */ - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, - value, - !(value & domain->bits.pxx), - 0, USEC_PER_MSEC); - if (ret) - dev_err(domain->dev, "failed to command PGC\n"); + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + value, + !(value & domain->bits.pxx), + 0, USEC_PER_MSEC); + if (ret) + dev_err(domain->dev, "failed to command PGC\n"); + } if (!IS_ERR(domain->regulator)) { ret = regulator_disable(domain->regulator); @@ -311,8 +320,9 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd) dev_err(domain->dev, "failed to disable regulator\n"); } - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, 0); + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); /* Disable all clocks */ for (i = 0; i < domain->num_clks; i++) -- 2.25.1