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From: Lee Jones <lee.jones@linaro.org>
To: Tom Rix <trix@redhat.com>
Cc: Russ Weight <russell.h.weight@intel.com>,
	linux-kernel@vger.kernel.org, lgoncalv@redhat.com,
	yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com
Subject: Re: [PATCH v9 1/1] mfd: intel-m10-bmc: support for MAX10 BMC Secure Updates
Date: Wed, 14 Apr 2021 17:25:18 +0100	[thread overview]
Message-ID: <20210414162518.GP4869@dell> (raw)
In-Reply-To: <c7044c0a-b3fb-837d-137f-fdb9b1d42847@redhat.com>

On Wed, 14 Apr 2021, Tom Rix wrote:

> 
> On 4/12/21 12:53 PM, Russ Weight wrote:
> > Add macros and definitions required by the MAX10 BMC
> > Secure Update driver.
> > 
> > Signed-off-by: Russ Weight <russell.h.weight@intel.com>
> > Acked-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > v9:
> >    - Rebased on next-20210412
> > v8:
> >    - Previously patch 1/6 in "Intel MAX10 BMC Secure Update Driver"
> >    - Rebased on next-20210121
> > v7:
> >    - No change
> > v6:
> >    - No change
> > v5:
> >    - Renamed USER_FLASH_COUNT to STAGING_FLASH_COUNT
> > v4:
> >    - No change
> > v3:
> >    - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure
> >      Update driver"
> >    - Removed wrapper functions (m10bmc_raw_*, m10bmc_sys_*). The
> >      underlying functions will be called directly.
> > v2:
> >    - These functions and macros were previously distributed among
> >      the patches that needed them. They are now grouped together
> >      in a single patch containing changes to the Intel MAX10 BMC
> >      driver.
> >    - Added DRBL_ prefix to some definitions
> >    - Some address definitions were moved here from the .c files that
> >      use them.
> > ---
> >   include/linux/mfd/intel-m10-bmc.h | 85 +++++++++++++++++++++++++++++++
> >   1 file changed, 85 insertions(+)
> > 
> > diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h
> > index c4eb38c13eda..f0044b14136e 100644
> > --- a/include/linux/mfd/intel-m10-bmc.h
> > +++ b/include/linux/mfd/intel-m10-bmc.h
> > @@ -16,6 +16,9 @@
> >   #define M10BMC_FLASH_END		0x1fffffff
> >   #define M10BMC_MEM_END			M10BMC_FLASH_END
> > +#define M10BMC_STAGING_BASE		0x18000000
> > +#define M10BMC_STAGING_SIZE		0x3800000
> > +
> >   /* Register offset of system registers */
> >   #define NIOS2_FW_VERSION		0x0
> >   #define M10BMC_MAC_LOW			0x10
> > @@ -33,6 +36,88 @@
> >   #define M10BMC_VER_PCB_INFO_MSK		GENMASK(31, 24)
> >   #define M10BMC_VER_LEGACY_INVALID	0xffffffff
> > +/* Secure update doorbell register, in system register region */
> > +#define M10BMC_DOORBELL			0x400
> 
> To be consistent with the existing register #defines,
> 
> The bit values for the register should follow the register and have a
> M10BMC_ prefix

This patch has been through 9 revisions and has been merged already.

Any changes will have to be submitted as subsequent patches.

-- 
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog

      reply	other threads:[~2021-04-14 16:25 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-12 19:53 [PATCH v9 0/1] Intel MAX10 BMC Macros for Secure Update Russ Weight
2021-04-12 19:53 ` [PATCH v9 1/1] mfd: intel-m10-bmc: support for MAX10 BMC Secure Updates Russ Weight
2021-04-14 10:05   ` Lee Jones
2021-04-14 15:51   ` Tom Rix
2021-04-14 16:25     ` Lee Jones [this message]

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