From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87BC1C433B4 for ; Tue, 20 Apr 2021 03:15:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A1C66101C for ; Tue, 20 Apr 2021 03:15:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234035AbhDTDP6 (ORCPT ); Mon, 19 Apr 2021 23:15:58 -0400 Received: from mail-oi1-f177.google.com ([209.85.167.177]:38405 "EHLO mail-oi1-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233632AbhDTDPs (ORCPT ); Mon, 19 Apr 2021 23:15:48 -0400 Received: by mail-oi1-f177.google.com with SMTP id d25so134439oij.5 for ; Mon, 19 Apr 2021 20:15:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aXUK1/r7k93rzxf4EUlsML+9TguQHlwah2y8W6FnseA=; b=WJZAlTYZ6y91MvKJ0U6U1UIheWu2NKbh7BpPEC5CF9gWk82yN1Oo/ILkdOUFGGqrGF lyJZJc8U+kljhIT8H3xTmKhSoFZicl5/ZowucPlPK9fKYLNJIr/bji57UqgzV41rQxxA y4yJLskX8JJiNxCzGALa5dMN8cwN6TrTR6EjVSsCZNkBhz4B96iYxpZJa5d9Ty1DS+Ks ZbY7OhZpfGrlrYU08Pa+Q2GgxVsanbJNlBxrljJhJ8s/rPFk2JGvvKdG/npkpLD+qjMq IG9SZz5PR3GPFenpwA8LkUkjjJEcG3xkmaE0GrSvToN1e97i6q3rlmgNSBn6zz7Cx3+2 YqNw== X-Gm-Message-State: AOAM530UZ8WbbsCUqvdgcrMqPqQPzsCAgIRWTqRYg6Tq0SiZDodhf23u +NxcFkAEMRM/wbve2X3fbQ== X-Google-Smtp-Source: ABdhPJxc6noVLD8p09Y2t8apB4dpVBJ9wZwwPuIYcud3i6iK2GH9f9h178dgJb9r9GD2Bh1MZE4swA== X-Received: by 2002:aca:cf09:: with SMTP id f9mr1581273oig.95.1618888517747; Mon, 19 Apr 2021 20:15:17 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id g16sm2347896oof.43.2021.04.19.20.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 20:15:16 -0700 (PDT) From: Rob Herring To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa , Mark Rutland Cc: Alexander Shishkin , honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/9] arm64: pmu: Add function implementation to update event index in userpage Date: Mon, 19 Apr 2021 22:15:04 -0500 Message-Id: <20210420031511.2348977-3-robh@kernel.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210420031511.2348977-1-robh@kernel.org> References: <20210420031511.2348977-1-robh@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Raphael Gault In order to be able to access the counter directly for userspace, we need to provide the index of the counter using the userpage. We thus need to override the event_idx function to retrieve and convert the perf_event index to armv8 hardware index. Since the arm_pmu driver can be used by any implementation, even if not armv8, two components play a role into making sure the behaviour is correct and consistent with the PMU capabilities: * the ARMPMU_EL0_RD_CNTR flag which denotes the capability to access counter from userspace. * the event_idx call back, which is implemented and initialized by the PMU implementation: if no callback is provided, the default behaviour applies, returning 0 as index value. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v7: - Add define ARMV8_IDX_CYCLE_COUNTER_USER for userspace index of cycle counter --- arch/arm64/kernel/perf_event.c | 20 +++++++++++++++++++- include/linux/perf/arm_pmu.h | 2 ++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4658fcf88c2b..40cf59455ce8 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -332,7 +332,7 @@ static const struct attribute_group armv8_pmuv3_caps_attr_group = { */ #define ARMV8_IDX_CYCLE_COUNTER 0 #define ARMV8_IDX_COUNTER0 1 - +#define ARMV8_IDX_CYCLE_COUNTER_USER 32 /* * We unconditionally enable ARMv8.5-PMU long event counter support @@ -871,6 +871,22 @@ static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc, clear_bit(idx - 1, cpuc->used_mask); } +static int armv8pmu_access_event_idx(struct perf_event *event) +{ + if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR)) + return 0; + + /* + * We remap the cycle counter index to 32 to + * match the offset applied to the rest of + * the counter indices. + */ + if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER) + return ARMV8_IDX_CYCLE_COUNTER_USER; + + return event->hw.idx; +} + /* * Add an event filter to a given event. */ @@ -1098,6 +1114,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, cpu_pmu->set_event_filter = armv8pmu_set_event_filter; cpu_pmu->filter_match = armv8pmu_filter_match; + cpu_pmu->pmu.event_idx = armv8pmu_access_event_idx; + cpu_pmu->name = name; cpu_pmu->map_event = map_event; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ? diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 505480217cf1..d29aa981d989 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -26,6 +26,8 @@ */ /* Event uses a 64bit counter */ #define ARMPMU_EVT_64BIT 1 +/* Allow access to hardware counter from userspace */ +#define ARMPMU_EL0_RD_CNTR 2 #define HW_OP_UNSUPPORTED 0xFFFF #define C(_x) PERF_COUNT_HW_CACHE_##_x -- 2.27.0