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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id g16sm2347896oof.43.2021.04.19.20.15.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 20:15:26 -0700 (PDT) From: Rob Herring To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa , Mark Rutland Cc: Alexander Shishkin , honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 8/9] perf: arm64: Add tests for 32-bit and 64-bit counter size userspace access Date: Mon, 19 Apr 2021 22:15:10 -0500 Message-Id: <20210420031511.2348977-9-robh@kernel.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210420031511.2348977-1-robh@kernel.org> References: <20210420031511.2348977-1-robh@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add arm64 specific tests for 32-bit and 64-bit counter user access. On arm64, counters default to 32-bit unless attr.config1:0 is set to 1. In order to enable user access for 64-bit counters, attr.config1 must be set to 3. Signed-off-by: Rob Herring --- v6: - New patch --- tools/perf/arch/arm64/include/arch-tests.h | 5 +++ tools/perf/arch/arm64/tests/arch-tests.c | 8 +++++ tools/perf/arch/arm64/tests/user-events.c | 38 ++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/tools/perf/arch/arm64/include/arch-tests.h b/tools/perf/arch/arm64/include/arch-tests.h index 380ad34a3f09..ddfa7460e1e1 100644 --- a/tools/perf/arch/arm64/include/arch-tests.h +++ b/tools/perf/arch/arm64/include/arch-tests.h @@ -15,5 +15,10 @@ extern struct test arch_tests[]; int test__rd_pinned(struct test __maybe_unused *test, int __maybe_unused subtest); +int test__rd_64bit(struct test __maybe_unused *test, + int __maybe_unused subtest); + +int test__rd_32bit(struct test __maybe_unused *test, + int __maybe_unused subtest); #endif diff --git a/tools/perf/arch/arm64/tests/arch-tests.c b/tools/perf/arch/arm64/tests/arch-tests.c index 80ce7bd3c16d..bbdb81aa3229 100644 --- a/tools/perf/arch/arm64/tests/arch-tests.c +++ b/tools/perf/arch/arm64/tests/arch-tests.c @@ -14,6 +14,14 @@ struct test arch_tests[] = { .desc = "Pinned CPU user counter access", .func = test__rd_pinned, }, + { + .desc = "User 64-bit counter access", + .func = test__rd_64bit, + }, + { + .desc = "User 32-bit counter access", + .func = test__rd_32bit, + }, { .func = NULL, }, diff --git a/tools/perf/arch/arm64/tests/user-events.c b/tools/perf/arch/arm64/tests/user-events.c index c8efc6b369e6..546323b5242c 100644 --- a/tools/perf/arch/arm64/tests/user-events.c +++ b/tools/perf/arch/arm64/tests/user-events.c @@ -175,3 +175,41 @@ int test__rd_pinned(struct test __maybe_unused *test, perf_evsel__delete(evsel); return ret; } + +static int test__rd_counter_size(struct test __maybe_unused *test, + int config1) +{ + int ret; + struct perf_evsel *evsel; + struct perf_event_attr attr = { + .type = PERF_TYPE_HARDWARE, + .config = PERF_COUNT_HW_INSTRUCTIONS, + .config1 = config1, + .exclude_kernel = 1, + }; + + if (!pmu_is_homogeneous()) + return TEST_SKIP; + + evsel = perf_init(&attr); + if (!evsel) + return -1; + + ret = run_test(evsel); + + perf_evsel__close(evsel); + perf_evsel__delete(evsel); + return ret; +} + +int test__rd_64bit(struct test __maybe_unused *test, + int __maybe_unused subtest) +{ + return test__rd_counter_size(test, 0x3); +} + +int test__rd_32bit(struct test __maybe_unused *test, + int __maybe_unused subtest) +{ + return test__rd_counter_size(test, 0x2); +} -- 2.27.0