Re: [PATCH v3] PCI: Disallow retraining link for Atheros chips on non-Gen1 PCIe bridges

Krzysztof Wilczyński
2021-06-01T11:28:28Z

Hi Pali,

Thank you for working on this and fixing the problem, and also thank you
goes to Marek and Toke for testing! Much appreciated!

[...]
> - AR9287 chip throws also Link Down and Link Up events, also has
> accessible config space containing correct values. But ath9k driver
> fails to initialize card from this state as it is unable to access HW
> registers. This also indicates that the chip iself is not able to read

A typo here - it would be "itself" in the above. But this is not worth
sending v4, and I am sure that Bjorn or Lorenzo could fix this in-place
when merging.

[...]
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Reported-by: Toke Høiland-Jørgensen <toke@redhat.com>
> Tested-by: Toke Høiland-Jørgensen <toke@redhat.com>
> Tested-by: Marek Behún <kabel@kernel.org>
[...]

Thank you everyone!

Reviewed-by: Krzysztof Wilczyński <kw@linux.com>

Krzysztof