From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12ADAC433ED for ; Fri, 30 Apr 2021 16:51:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E2888613D9 for ; Fri, 30 Apr 2021 16:51:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230473AbhD3QwK (ORCPT ); Fri, 30 Apr 2021 12:52:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229750AbhD3QwI (ORCPT ); Fri, 30 Apr 2021 12:52:08 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5586C06174A; Fri, 30 Apr 2021 09:51:19 -0700 (PDT) Received: from localhost (unknown [IPv6:2a01:e0a:2c:6930:5cf4:84a1:2763:fe0d]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: bbrezillon) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id BD3CF1F43BCF; Fri, 30 Apr 2021 17:51:17 +0100 (BST) Date: Fri, 30 Apr 2021 18:51:04 +0200 From: Boris Brezillon Cc: , Mark Brown , Miquel Raynal , Vignesh Raghavendra , , Alexandre Torgue , , , , , Subject: Re: [PATCH 1/3] spi: spi-mem: add automatic poll status functions Message-ID: <20210430185104.377d1bc6@collabora.com> In-Reply-To: <20210426143934.25275-2-patrice.chotard@foss.st.com> References: <20210426143934.25275-1-patrice.chotard@foss.st.com> <20210426143934.25275-2-patrice.chotard@foss.st.com> Organization: Collabora X-Mailer: Claws Mail 3.17.8 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 26 Apr 2021 16:39:32 +0200 wrote: > From: Christophe Kerello > > With STM32 QSPI, it is possible to poll the status register of the device. > This could be done to offload the CPU during an operation (erase or > program a SPI NAND for example). > > spi_mem_poll_status API has been added to handle this feature. > > Signed-off-by: Christophe Kerello > Signed-off-by: Patrice Chotard > --- > drivers/spi/spi-mem.c | 34 ++++++++++++++++++++++++++++++++++ > include/linux/spi/spi-mem.h | 8 ++++++++ > 2 files changed, 42 insertions(+) > > diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c > index 1513553e4080..43dce4b0efa4 100644 > --- a/drivers/spi/spi-mem.c > +++ b/drivers/spi/spi-mem.c > @@ -743,6 +743,40 @@ static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv) > return container_of(drv, struct spi_mem_driver, spidrv.driver); > } > > +/** > + * spi_mem_poll_status() - Poll memory device status > + * @mem: SPI memory device > + * @op: the memory operation to execute > + * @mask: status bitmask to ckeck > + * @match: status expected value > + * @timeout: timeout > + * > + * This function send a polling status request to the controller driver > + * > + * Return: 0 in case of success, -ETIMEDOUT in case of error, > + * -EOPNOTSUPP if not supported. > + */ > +int spi_mem_poll_status(struct spi_mem *mem, > + const struct spi_mem_op *op, > + u8 mask, u8 match, u16 timeout) > +{ > + struct spi_controller *ctlr = mem->spi->controller; > + int ret = -EOPNOTSUPP; > + > + if (ctlr->mem_ops && ctlr->mem_ops->poll_status) { > + ret = spi_mem_access_start(mem); You should probably check that op is a single byte read before accepting the command. > + if (ret) > + return ret; > + > + ret = ctlr->mem_ops->poll_status(mem, op, mask, match, timeout); You also need some sort of ->poll_status_is_supported() to validate that the controller supports the status polling for this specific op (I can imagine some controllers having a limit on the number of dummy cycles/address bytes). I guess you could just fall back on SW-based status polling if ctlr->mem_ops->poll_status() returns -ENOTSUPP. > + > + spi_mem_access_end(mem); > + } > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(spi_mem_poll_status); > + > static int spi_mem_probe(struct spi_device *spi) > { > struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); > diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h > index 2b65c9edc34e..5f78917c0f68 100644 > --- a/include/linux/spi/spi-mem.h > +++ b/include/linux/spi/spi-mem.h > @@ -250,6 +250,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem) > * the currently mapped area), and the caller of > * spi_mem_dirmap_write() is responsible for calling it again in > * this case. > + * @poll_status: poll memory device status > * > * This interface should be implemented by SPI controllers providing an > * high-level interface to execute SPI memory operation, which is usually the > @@ -274,6 +275,9 @@ struct spi_controller_mem_ops { > u64 offs, size_t len, void *buf); > ssize_t (*dirmap_write)(struct spi_mem_dirmap_desc *desc, > u64 offs, size_t len, const void *buf); > + int (*poll_status)(struct spi_mem *mem, > + const struct spi_mem_op *op, > + u8 mask, u8 match, u16 timeout); > }; > > /** > @@ -369,6 +373,10 @@ devm_spi_mem_dirmap_create(struct device *dev, struct spi_mem *mem, > void devm_spi_mem_dirmap_destroy(struct device *dev, > struct spi_mem_dirmap_desc *desc); > > +int spi_mem_poll_status(struct spi_mem *mem, > + const struct spi_mem_op *op, > + u8 mask, u8 match, u16 timeout); > + > int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv, > struct module *owner); >