From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0048C433B4 for ; Mon, 3 May 2021 10:58:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93D58611CB for ; Mon, 3 May 2021 10:58:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233494AbhECK7X (ORCPT ); Mon, 3 May 2021 06:59:23 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:51020 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233477AbhECK7W (ORCPT ); Mon, 3 May 2021 06:59:22 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 143Akm0o036864; Mon, 3 May 2021 18:46:48 +0800 (GMT-8) (envelope-from steven_lee@aspeedtech.com) Received: from aspeedtech.com (192.168.100.253) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 18:58:27 +0800 Date: Mon, 3 May 2021 18:58:19 +0800 From: Steven Lee To: Andrew Jeffery CC: Rob Herring , Joel Stanley , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list , Hongwei Zhang , Ryan Chen , Chin-Ting Kuo Subject: Re: [PATCH v2 2/3] ARM: dts: aspeed: ast2600evb: Add timing-phase property for eMMC controller Message-ID: <20210503105819.GC12520@aspeedtech.com> References: <20210503014336.20256-1-steven_lee@aspeedtech.com> <20210503014336.20256-3-steven_lee@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [192.168.100.253] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 143Akm0o036864 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The 05/03/2021 13:07, Andrew Jeffery wrote: > Hi Steven, > > On Mon, 3 May 2021, at 11:13, Steven Lee wrote: > > Set eMMC input clock phase to 3, which is more stable on AST2600 EVBs. > > > > Signed-off-by: Steven Lee > > --- > > arch/arm/boot/dts/aspeed-ast2600-evb.dts | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts > > b/arch/arm/boot/dts/aspeed-ast2600-evb.dts > > index 2772796e215e..7a93317e27dc 100644 > > --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts > > +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts > > @@ -102,6 +102,7 @@ > > > > &emmc_controller { > > status = "okay"; > > + timing-phase = <0x300FF>; > > Please use the existing binding for phase corrections. The existing > binding is already supported by the driver (added in v5.12). > Hi Andrew, Thanks for the review. I will add the following settings from aspeed-bmc-ibm-rainier.dts instead of adding timing-phase in device tree. clk-phase-mmc-hs200 = ; > Andrew