Re: [PATCH 13/16] clk: renesas: Add CPG core wrapper for RZ/G2L SoC

Geert Uytterhoeven
2021-05-27T12:04:56Z

Hi Prabhakar,

On Fri, May 14, 2021 at 9:24 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add CPG core wrapper for RZ/G2L family.
>
> Based on a patch in the BSP by Binh Nguyen
> <binh.nguyen.jz@renesas.com>.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

> --- /dev/null
> +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c

> +static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
> +{
> + struct mstp_clock *clock = to_mod_clock(hw);
> + struct cpg_mssr_priv *priv = clock->priv;
> + unsigned int reg = MSSR_OFF(clock->bit) * 4;

The "* 4" here makes it difficult to review the module clock tables.

E.g.

DEF_MOD("gic", R9A07G044_CLK_GIC600,
R9A07G044_CLK_P1,
MSSR(5, BIT(0), (BIT(0) | BIT(1)))),

The "5" means the CLK_ON_GIC600 register is at offset CLK_ON_R(5 * 4)
= 0x514. Removing the "* 4" means you could use
"MSSR(0x14, BIT(0), (BIT(0) | BIT(1))" instead.

Unless it has unpleasant side effects, I'd even consider putting
the full CLK_ON offset there, i.e.
"MSSR(0x514, BIT(0), (BIT(0) | BIT(1))" and change the macros like:

#define CLK_ON_R(reg) (reg)
#define CLK_MON_R(reg) (0x680 - 0x500 + (reg))

> --- /dev/null
> +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h

> +#define CLK_ON_R(reg) (0x500 + reg)
> +#define CLK_MON_R(reg) (0x680 + reg)
> +#define CLK_RST_R(reg) (0x800 + reg)
> +#define CLK_MRST_R(reg) (0x980 + reg)

The last three don't seem to be documented?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds