From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1C17C47089 for ; Mon, 24 May 2021 14:50:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D75AC61606 for ; Mon, 24 May 2021 14:50:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233591AbhEXOwL (ORCPT ); Mon, 24 May 2021 10:52:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:54514 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233298AbhEXOs7 (ORCPT ); Mon, 24 May 2021 10:48:59 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 880C0613DF; Mon, 24 May 2021 14:47:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621867642; bh=eThF42QgHM2ceyuUbfHXSeQsf1W1pocY7rix57lF/sE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pmdJlSJ6MA7kxbZB3wbI+cVHfiKwHePXXq5fcd9uaqHHxTV3PYjIu1Le/1na+ifW5 8luPMFPMqIaXnT7BvF6UKF2U141RtNSVQ9DC8EAVHl13cQUC11cwfNcBmozTVaKjAi ofMqPef6cbgLXaoeZ04L6toclCEs3uBrVC5k2dMpev5Nzbo8ebu3O89U/WCtmSOJ5J zZpIsfpz9EK1ihlxh3j8IuZtq31T+6uERk83yedzoZumsrYbFEsjOh9tsyY6j6PRr/ KJtKPLzZ0NiVJHXpUEDAcuQ7GFd5lK+dMBC3cwVEppAj4tJOm73yQs7V7r4NPdW9Xl bY7ikBeosuhSg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Peter Zijlstra , Stafford Horne , Sasha Levin , openrisc@lists.librecores.org Subject: [PATCH AUTOSEL 5.12 47/63] openrisc: Define memory barrier mb Date: Mon, 24 May 2021 10:46:04 -0400 Message-Id: <20210524144620.2497249-47-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210524144620.2497249-1-sashal@kernel.org> References: <20210524144620.2497249-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Peter Zijlstra [ Upstream commit 8b549c18ae81dbc36fb11e4aa08b8378c599ca95 ] This came up in the discussion of the requirements of qspinlock on an architecture. OpenRISC uses qspinlock, but it was noticed that the memmory barrier was not defined. Peter defined it in the mail thread writing: As near as I can tell this should do. The arch spec only lists this one instruction and the text makes it sound like a completion barrier. This is correct so applying this patch. Signed-off-by: Peter Zijlstra [shorne@gmail.com:Turned the mail into a patch] Signed-off-by: Stafford Horne Signed-off-by: Sasha Levin --- arch/openrisc/include/asm/barrier.h | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 arch/openrisc/include/asm/barrier.h diff --git a/arch/openrisc/include/asm/barrier.h b/arch/openrisc/include/asm/barrier.h new file mode 100644 index 000000000000..7538294721be --- /dev/null +++ b/arch/openrisc/include/asm/barrier.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_BARRIER_H +#define __ASM_BARRIER_H + +#define mb() asm volatile ("l.msync" ::: "memory") + +#include + +#endif /* __ASM_BARRIER_H */ -- 2.30.2