From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: <ira.weiny@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 4/5] cxl/mem: Reserve individual register block regions
Date: Tue, 25 May 2021 10:59:37 +0100 [thread overview]
Message-ID: <20210525105937.00000696@Huawei.com> (raw)
In-Reply-To: <20210522001154.2680157-5-ira.weiny@intel.com>
On Fri, 21 May 2021 17:11:53 -0700
<ira.weiny@intel.com> wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> Now that individual register blocks are mapped; those blocks regions
> should be reserved individually.
>
> Remove general pci device management and create managed region
> reservations based on the individual register blocks.
Would be good to include a bit more of the 'reason why' in the actual
patch descriptions. Afterall, who ever goes looking for the cover letter
after patches are applied ;)
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> Changes for V2:
> New patch
> ---
> drivers/cxl/core.c | 36 ++++++++++++++++++++++++++++++++----
> drivers/cxl/pci.c | 6 ++----
> 2 files changed, 34 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
> index add66a6ec875..ae38f17be1e7 100644
> --- a/drivers/cxl/core.c
> +++ b/drivers/cxl/core.c
> @@ -74,11 +74,33 @@ void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> }
> EXPORT_SYMBOL_GPL(cxl_probe_device_regs);
>
> +static void __iomem *cxl_ioremap_block(struct pci_dev *pdev,
> + resource_size_t addr,
> + resource_size_t length)
> +{
> + struct device *dev = &pdev->dev;
> + void __iomem *ret_val;
> + struct resource *res;
> +
> + res = devm_request_mem_region(dev, addr, length, pci_name(pdev));
> + if (!res) {
> + dev_err(dev, "Failed to request region %#llx-%#llx\n",
> + addr, addr+length);
> + return NULL;
> + }
> +
> + ret_val = devm_ioremap(dev, addr, length);
> + if (!ret_val)
> + dev_err(dev, "Failed to map region %#llx-%#llx\n",
> + addr, addr+length);
> +
> + return ret_val;
> +}
> +
> int cxl_map_device_regs(struct pci_dev *pdev,
> struct cxl_device_regs *regs,
> struct cxl_register_map *map)
> {
> - struct device *dev = &pdev->dev;
> resource_size_t phys_addr;
>
> phys_addr = pci_resource_start(pdev, map->barno);
> @@ -90,7 +112,9 @@ int cxl_map_device_regs(struct pci_dev *pdev,
>
> addr = phys_addr + map->device_map.status.offset;
> length = map->device_map.status.size;
> - regs->status = devm_ioremap(dev, addr, length);
> + regs->status = cxl_ioremap_block(pdev, addr, length);
> + if (!regs->status)
> + return -ENOMEM;
> }
>
> if (map->device_map.mbox.valid) {
> @@ -99,7 +123,9 @@ int cxl_map_device_regs(struct pci_dev *pdev,
>
> addr = phys_addr + map->device_map.mbox.offset;
> length = map->device_map.mbox.size;
> - regs->mbox = devm_ioremap(dev, addr, length);
> + regs->mbox = cxl_ioremap_block(pdev, addr, length);
> + if (!regs->mbox)
> + return -ENOMEM;
> }
>
> if (map->device_map.memdev.valid) {
> @@ -108,7 +134,9 @@ int cxl_map_device_regs(struct pci_dev *pdev,
>
> addr = phys_addr + map->device_map.memdev.offset;
> length = map->device_map.memdev.size;
> - regs->memdev = devm_ioremap(dev, addr, length);
> + regs->memdev = cxl_ioremap_block(pdev, addr, length);
> + if (!regs->memdev)
> + return -ENOMEM;
> }
>
> return 0;
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 3ffd5fad74b4..776cb8e28c2d 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -1110,6 +1110,8 @@ static int cxl_mem_setup_regs(struct cxl_mem *cxlm)
> goto free_maps;
> }
>
> + pci_release_mem_regions(pdev);
> +
> list_for_each_entry(map, ®ister_maps, list) {
> ret = cxl_map_regs(cxlm, map);
> if (ret)
> @@ -1547,10 +1549,6 @@ static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> struct cxl_mem *cxlm;
> int rc;
>
> - rc = pcim_enable_device(pdev);
> - if (rc)
> - return rc;
> -
> cxlm = cxl_mem_create(pdev);
> if (IS_ERR(cxlm))
> return PTR_ERR(cxlm);
next prev parent reply other threads:[~2021-05-25 10:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-22 0:11 [PATCH v2 0/5] Map register blocks individually ira.weiny
2021-05-22 0:11 ` [PATCH v2 1/5] cxl/mem: Introduce cxl_decode_register_block() ira.weiny
2021-05-25 9:53 ` Jonathan Cameron
2021-05-22 0:11 ` [PATCH v2 2/5] cxl/mem: Reserve all device regions at once ira.weiny
2021-05-25 9:54 ` Jonathan Cameron
2021-05-22 0:11 ` [PATCH v2 3/5] cxl/mem: Map registers based on capabilities ira.weiny
2021-05-25 9:52 ` Jonathan Cameron
2021-05-27 17:53 ` Ira Weiny
2021-05-22 0:11 ` [PATCH v2 4/5] cxl/mem: Reserve individual register block regions ira.weiny
2021-05-25 9:59 ` Jonathan Cameron [this message]
2021-05-22 0:11 ` [PATCH v2 5/5] cxl: Add HDM decoder capbilities ira.weiny
2021-05-25 14:28 ` Jonathan Cameron
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