* [PATCH 2/2] soc: mediatek: SVS: add mt8195 SVS GPU driver
2021-07-13 2:05 [PATCH 0/2] soc: mediatek: SVS: add mt8195 SVS GPU driver YT Lee
2021-07-13 2:05 ` [PATCH 1/2] dt-bindings: soc: mediatek: add mt8195 svs dt-bindings YT Lee
@ 2021-07-13 2:05 ` YT Lee
1 sibling, 0 replies; 4+ messages in thread
From: YT Lee @ 2021-07-13 2:05 UTC (permalink / raw)
To: yt.lee, roger.lu, matthias.bgg, eballetbo, khilman, robh+dt,
drinkcat, sboyd, p.zabel
Cc: srv_heupstream, fan.chen, xiaoqing.liu, charles.yang, angus.lin,
mark.rutland, nm, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-pm, Project_Global_Chrome_Upstream_Group,
linux, louis.yu
To support SVS GPU on mt8195, add corresponding
bank information, platform data and parsing function.
Signed-off-by: YT Lee <yt.lee@mediatek.com>
---
This patch depends on "soc: mediatek: SVS: introduce MTK SVS"[1],
also refine svs_suspend, svs_resume functions according to [2].
[1]http://lists.infradead.org/pipermail/linux-mediatek/2021-July/026270.html
[2]http://lists.infradead.org/pipermail/linux-mediatek/2021-July/026282.html
drivers/soc/mediatek/mtk-svs.c | 228 +++++++++++++++++++++++++++++++--
1 file changed, 216 insertions(+), 12 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
index 67f1ea23ea0a..2a07d79d24cb 100644
--- a/drivers/soc/mediatek/mtk-svs.c
+++ b/drivers/soc/mediatek/mtk-svs.c
@@ -1440,6 +1440,88 @@ static int svs_resource_setup(struct svs_platform *svsp)
return 0;
}
+static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp)
+{
+ struct svs_bank *svsb;
+ struct nvmem_cell *cell;
+ u32 idx, i, ft_pgm, vmin, golden_temp;
+
+ for (i = 0; i < svsp->efuse_num; i++)
+ if (svsp->efuse[i])
+ dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
+ i, svsp->efuse[i]);
+
+ /* Svs efuse parsing */
+ ft_pgm = svsp->efuse[0] & GENMASK(7, 0);
+ vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0);
+
+ for (idx = 0; idx < svsp->bank_num; idx++) {
+ svsb = &svsp->banks[idx];
+
+ if (svsb->sw_id != SVSB_GPU)
+ return false;
+
+ if (vmin == 0x1)
+ svsb->vmin = 0x1e;
+
+ if (ft_pgm == 0)
+ svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
+
+ if (svsb->type == SVSB_LOW) {
+ svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0);
+ svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0);
+ svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0);
+ svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0);
+ svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0);
+ svsb->vmax += svsb->dvt_fixed;
+ } else if (svsb->type == SVSB_HIGH) {
+ svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0);
+ svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0);
+ svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0);
+ svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0);
+ svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0);
+ svsb->vmax += svsb->dvt_fixed;
+ }
+ }
+
+ /* Thermal efuse parsing */
+ cell = nvmem_cell_get(svsp->dev, "t-calibration-data");
+ if (IS_ERR_OR_NULL(cell)) {
+ dev_err(svsp->dev, "no thermal cell, no mon mode\n");
+ for (idx = 0; idx < svsp->bank_num; idx++) {
+ svsb = &svsp->banks[idx];
+ svsb->mode_support &= ~SVSB_MODE_MON;
+ }
+
+ return true;
+ }
+
+ svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_num);
+ svsp->tefuse_num /= sizeof(u32);
+ nvmem_cell_put(cell);
+
+ for (i = 0; i < svsp->tefuse_num; i++)
+ if (svsp->tefuse[i] != 0)
+ break;
+
+ if (i == svsp->tefuse_num)
+ golden_temp = 50; /* All thermal efuse data are 0 */
+ else
+ golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0);
+
+ for (idx = 0; idx < svsp->bank_num; idx++) {
+ svsb = &svsp->banks[idx];
+
+ if (svsb->sw_id != SVSB_GPU)
+ return false;
+
+ svsb->mts = 500;
+ svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4;
+ }
+
+ return true;
+}
+
static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp)
{
struct svs_bank *svsb;
@@ -1771,12 +1853,10 @@ static int svs_suspend(struct device *dev)
}
}
- if (svsp->rst) {
- ret = reset_control_assert(svsp->rst);
- if (ret) {
- dev_err(svsp->dev, "cannot assert reset %d\n", ret);
- return ret;
- }
+ ret = reset_control_assert(svsp->rst);
+ if (ret) {
+ dev_err(svsp->dev, "cannot assert reset %d\n", ret);
+ return ret;
}
clk_disable_unprepare(svsp->main_clk);
@@ -1797,12 +1877,10 @@ static int svs_resume(struct device *dev)
return ret;
}
- if (svsp->rst) {
- ret = reset_control_deassert(svsp->rst);
- if (ret) {
- dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
- return ret;
- }
+ ret = reset_control_deassert(svsp->rst);
+ if (ret) {
+ dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
+ return ret;
}
for (idx = 0; idx < svsp->bank_num; idx++) {
@@ -2081,6 +2159,89 @@ static int svs_create_svs_debug_cmds(struct svs_platform *svsp)
return 0;
}
+static struct svs_bank svs_mt8195_banks[] = {
+ {
+ .sw_id = SVSB_GPU,
+ .set_freqs_pct = svs_set_freqs_pct_v3,
+ .get_vops = svs_get_vops_v3,
+ .hw_id = 0,
+ .tzone_name = "gpu1",
+ .buck_name = "mali",
+ .volt_flags = SVSB_INIT02_RM_DVTFIXED |
+ SVSB_MON_VOLT_IGNORE,
+ .mode_support = SVSB_MODE_INIT02,
+ .opp_count = 16,
+ .freq_base = 640000000,
+ .turn_freq_base = 640000000,
+ .vboot = 0x38,
+ .volt_step = 6250,
+ .volt_base = 400000,
+ .volt_offset = 0,
+ .vmax = 0x38,
+ .vmin = 0x14,
+ .dthi = 0x1,
+ .dtlo = 0xfe,
+ .det_window = 0xa28,
+ .det_max = 0xffff,
+ .age_config = 0x555555,
+ .agem = 0,
+ .dc_config = 0x1,
+ .dvt_fixed = 0x1,
+ .vco = 0x18,
+ .chk_shift = 0x87,
+ .temp_upper_bound = 0x64,
+ .temp_lower_bound = 0xb2,
+ .tzone_high_temp = 85000,
+ .tzone_high_temp_offset = 0,
+ .tzone_low_temp = 25000,
+ .tzone_low_temp_offset = 7,
+ .core_sel = 0x0fff0100,
+ .int_st = BIT(0),
+ .ctl0 = 0x00540003,
+ .type = SVSB_LOW,
+ },
+ {
+ .sw_id = SVSB_GPU,
+ .set_freqs_pct = svs_set_freqs_pct_v3,
+ .get_vops = svs_get_vops_v3,
+ .hw_id = 1,
+ .tzone_name = "gpu1",
+ .buck_name = "mali",
+ .volt_flags = SVSB_INIT02_RM_DVTFIXED |
+ SVSB_MON_VOLT_IGNORE,
+ .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
+ .opp_count = 16,
+ .freq_base = 880000000,
+ .turn_freq_base = 640000000,
+ .vboot = 0x38,
+ .volt_step = 6250,
+ .volt_base = 400000,
+ .volt_offset = 0,
+ .vmax = 0x38,
+ .vmin = 0x14,
+ .dthi = 0x1,
+ .dtlo = 0xfe,
+ .det_window = 0xa28,
+ .det_max = 0xffff,
+ .age_config = 0x555555,
+ .agem = 0,
+ .dc_config = 0x1,
+ .dvt_fixed = 0x6,
+ .vco = 0x18,
+ .chk_shift = 0x87,
+ .temp_upper_bound = 0x64,
+ .temp_lower_bound = 0xb2,
+ .tzone_high_temp = 85000,
+ .tzone_high_temp_offset = 0,
+ .tzone_low_temp = 25000,
+ .tzone_low_temp_offset = 7,
+ .core_sel = 0x0fff0101,
+ .int_st = BIT(1),
+ .ctl0 = 0x00540003,
+ .type = SVSB_HIGH,
+ },
+};
+
static struct svs_bank svs_mt8192_banks[] = {
{
.sw_id = SVSB_GPU,
@@ -2318,6 +2479,46 @@ static struct svs_bank svs_mt8183_banks[] = {
},
};
+static int svs_get_svs_mt8195_platform_data(struct svs_platform *svsp)
+{
+ struct device *dev;
+ struct svs_bank *svsb;
+ u32 idx;
+
+ svsp->name = "mt8195-svs";
+ svsp->banks = svs_mt8195_banks;
+ svsp->efuse_parsing = svs_mt8195_efuse_parsing;
+ svsp->regs = svs_regs_v2;
+ svsp->irqflags = IRQF_TRIGGER_HIGH;
+ svsp->bank_num = ARRAY_SIZE(svs_mt8195_banks);
+ svsp->efuse_check = 10;
+
+ svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
+ if (IS_ERR(svsp->rst)) {
+ dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
+ "cannot get svs reset control\n");
+ return PTR_ERR(svsp->rst);
+ }
+
+ dev = svs_add_device_link(svsp, "lvts");
+ if (IS_ERR(dev))
+ return PTR_ERR(dev);
+
+ for (idx = 0; idx < svsp->bank_num; idx++) {
+ svsb = &svsp->banks[idx];
+
+ if (svsb->type == SVSB_HIGH)
+ svsb->opp_dev = svs_add_device_link(svsp, "mali");
+ else if (svsb->type == SVSB_LOW)
+ svsb->opp_dev = svs_get_subsys_device(svsp, "mali");
+
+ if (IS_ERR(svsb->opp_dev))
+ return PTR_ERR(svsb->opp_dev);
+ }
+
+ return 0;
+}
+
static int svs_get_svs_mt8192_platform_data(struct svs_platform *svsp)
{
struct device *dev;
@@ -2414,6 +2615,9 @@ static const struct of_device_id mtk_svs_of_match[] = {
}, {
.compatible = "mediatek,mt8192-svs",
.data = &svs_get_svs_mt8192_platform_data,
+ }, {
+ .compatible = "mediatek,mt8195-svs",
+ .data = &svs_get_svs_mt8195_platform_data,
}, {
/* Sentinel */
},
--
2.18.0
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