From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D29BAC4320E for ; Thu, 12 Aug 2021 19:02:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B1548610A3 for ; Thu, 12 Aug 2021 19:02:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235193AbhHLTDM (ORCPT ); Thu, 12 Aug 2021 15:03:12 -0400 Received: from mail.kernel.org ([198.145.29.99]:59380 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235117AbhHLTDA (ORCPT ); Thu, 12 Aug 2021 15:03:00 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1EAE76109D; Thu, 12 Aug 2021 19:02:35 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mEFyL-004c9r-FF; Thu, 12 Aug 2021 20:02:33 +0100 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Will Deacon , Catalin Marinas , Mark Rutland , Ard Biesheuvel , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, kernel-team@android.com Subject: [PATCH 5/5] arm64: Document the requirement for SCR_EL3.HCE Date: Thu, 12 Aug 2021 20:02:13 +0100 Message-Id: <20210812190213.2601506-6-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210812190213.2601506-1-maz@kernel.org> References: <20210812190213.2601506-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zajec5@gmail.com, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ardb@kernel.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It is amazing that we never documented this absolutely basic requirement: if you boot the kernel at EL2, you'd better enable the HVC instruction from EL3. Really, just do it. Signed-off-by: Marc Zyngier --- Documentation/arm64/booting.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index a9192e7a231b..6c729d0c4bc2 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -212,6 +212,11 @@ Before jumping into the kernel, the following conditions must be met: - The value of SCR_EL3.FIQ must be the same as the one present at boot time whenever the kernel is executing. + For all systems: + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.HCE (bit 8) must be initialised to 0b1. + For systems with a GICv3 interrupt controller to be used in v3 mode: - If EL3 is present: -- 2.30.2