From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBD91C4338F for ; Tue, 24 Aug 2021 10:49:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A472B61245 for ; Tue, 24 Aug 2021 10:49:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236392AbhHXKtv (ORCPT ); Tue, 24 Aug 2021 06:49:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:36980 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236365AbhHXKtt (ORCPT ); Tue, 24 Aug 2021 06:49:49 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 0597C61248; Tue, 24 Aug 2021 10:49:03 +0000 (UTC) Date: Tue, 24 Aug 2021 11:49:01 +0100 From: Catalin Marinas To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= , Will Deacon , Mark Rutland , Ard Biesheuvel , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, kernel-team@android.com Subject: Re: [PATCH 5/5] arm64: Document the requirement for SCR_EL3.HCE Message-ID: <20210824104900.GB623@arm.com> References: <20210812190213.2601506-1-maz@kernel.org> <20210812190213.2601506-6-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210812190213.2601506-6-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 12, 2021 at 08:02:13PM +0100, Marc Zyngier wrote: > It is amazing that we never documented this absolutely basic > requirement: if you boot the kernel at EL2, you'd better > enable the HVC instruction from EL3. > > Really, just do it. > > Signed-off-by: Marc Zyngier > --- > Documentation/arm64/booting.rst | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst > index a9192e7a231b..6c729d0c4bc2 100644 > --- a/Documentation/arm64/booting.rst > +++ b/Documentation/arm64/booting.rst > @@ -212,6 +212,11 @@ Before jumping into the kernel, the following conditions must be met: > - The value of SCR_EL3.FIQ must be the same as the one present at boot > time whenever the kernel is executing. > > + For all systems: > + - If EL3 is present and the kernel is entered at EL2: > + > + - SCR_EL3.HCE (bit 8) must be initialised to 0b1. > + > For systems with a GICv3 interrupt controller to be used in v3 mode: > - If EL3 is present: I'll queue this patch only for now. A nitpick, I think we should move "For all systems" and "If EL3 is present..." above the lines describing the SCR_EL3.FIQ requirement (I can make the change locally). -- Catalin