From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-24.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFC56C432BE for ; Tue, 24 Aug 2021 17:35:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB62C60231 for ; Tue, 24 Aug 2021 17:35:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239490AbhHXRgH (ORCPT ); Tue, 24 Aug 2021 13:36:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:40392 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241975AbhHXReV (ORCPT ); Tue, 24 Aug 2021 13:34:21 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id B9C2561B94; Tue, 24 Aug 2021 17:06:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629824794; bh=qmQqzTEJfNzK7rqfXI5gxYXe3mcQYZp1m3Afc9zhmRA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MZc2NW3EX8WINh5ufmAOk/6S8ZZw3BXFNpbgq97fyDjChfioK3kumW035j09qAnf2 mh8eq3H7c754XHkQk/MFRcuBDd8ErKLj9cAkx+L3BAv8HPAnUHwWYWscy6+l7r/kdE sOBGXM8T9elC3/xKnfAAOhFITSF3EalE9wdFpg90Hrt7Na2B1y6fjuhV8VXXhU8+qJ LnvPlpaYaxtBhmKNwPlSS46JkE0EB8pO648yDRSUjOB1JvH1mwjHxxxUejmLjLIYh/ iBdxZPLVhdRQ9Yf6rJsA+2NJGpHslr3MPYXpoBPyVgDUDnhe5IUBUGRSaUuu0NYADd oI/+6LUbQqOOg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Thomas Gleixner , Marc Zyngier , Bjorn Helgaas , Greg Kroah-Hartman Subject: [PATCH 4.9 18/43] PCI/MSI: Enforce MSI[X] entry updates to be visible Date: Tue, 24 Aug 2021 13:05:49 -0400 Message-Id: <20210824170614.710813-19-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210824170614.710813-1-sashal@kernel.org> References: <20210824170614.710813-1-sashal@kernel.org> MIME-Version: 1.0 X-KernelTest-Patch: http://kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.9.281-rc1.gz X-KernelTest-Tree: git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git X-KernelTest-Branch: linux-4.9.y X-KernelTest-Patches: git://git.kernel.org/pub/scm/linux/kernel/git/stable/stable-queue.git X-KernelTest-Version: 4.9.281-rc1 X-KernelTest-Deadline: 2021-08-26T17:06+00:00 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thomas Gleixner commit b9255a7cb51754e8d2645b65dd31805e282b4f3e upstream. Nothing enforces the posted writes to be visible when the function returns. Flush them even if the flush might be redundant when the entry is masked already as the unmask will flush as well. This is either setup or a rare affinity change event so the extra flush is not the end of the world. While this is more a theoretical issue especially the logic in the X86 specific msi_set_affinity() function relies on the assumption that the update has reached the hardware when the function returns. Again, as this never has been enforced the Fixes tag refers to a commit in: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Fixes: f036d4ea5fa7 ("[PATCH] ia32 Message Signalled Interrupt support") Signed-off-by: Thomas Gleixner Tested-by: Marc Zyngier Reviewed-by: Marc Zyngier Acked-by: Bjorn Helgaas Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20210729222542.515188147@linutronix.de Signed-off-by: Greg Kroah-Hartman --- drivers/pci/msi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 3be9c0ceb4e9..77810f424049 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -341,6 +341,9 @@ void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) if (unmasked) __pci_msix_desc_mask_irq(entry, 0); + + /* Ensure that the writes are visible in the device */ + readl(base + PCI_MSIX_ENTRY_DATA); } else { int pos = dev->msi_cap; u16 msgctl; @@ -361,6 +364,8 @@ void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) pci_write_config_word(dev, pos + PCI_MSI_DATA_32, msg->data); } + /* Ensure that the writes are visible in the device */ + pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); } entry->msg = *msg; } -- 2.30.2