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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id 132sm11758750pfy.190.2021.09.14.21.45.57 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 Sep 2021 21:45:58 -0700 (PDT) Date: Tue, 14 Sep 2021 21:38:06 -0700 From: Nicolin Chen To: Dmitry Osipenko Cc: thierry.reding@gmail.com, joro@8bytes.org, will@kernel.org, vdumpa@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 6/6] iommu/tegra-smmu: Add pagetable mappings to debugfs Message-ID: <20210915043806.GA19185@Asurada-Nvidia> References: <20210914013858.31192-1-nicoleotsuka@gmail.com> <20210914013858.31192-7-nicoleotsuka@gmail.com> <31501a62-3312-9f04-3bb8-790d0481746c@gmail.com> <20210914184933.GA32705@Asurada-Nvidia> <25d68aff-323a-df54-45f9-55b22f3089e0@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <25d68aff-323a-df54-45f9-55b22f3089e0@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 14, 2021 at 10:20:30PM +0300, Dmitry Osipenko wrote: > 14.09.2021 21:49, Nicolin Chen пишет: > > On Tue, Sep 14, 2021 at 04:29:15PM +0300, Dmitry Osipenko wrote: > >> 14.09.2021 04:38, Nicolin Chen пишет: > >>> +static unsigned long pd_pt_index_iova(unsigned int pd_index, unsigned int pt_index) > >>> +{ > >>> + return ((dma_addr_t)pd_index & (SMMU_NUM_PDE - 1)) << SMMU_PDE_SHIFT | > >>> + ((dma_addr_t)pt_index & (SMMU_NUM_PTE - 1)) << SMMU_PTE_SHIFT; > >>> +} > >> > >> We know that IOVA is fixed to u32 for this controller. Can we avoid all > >> these dma_addr_t castings? It should make code cleaner a tad, IMO. > > > > Tegra210 actually supports 34-bit IOVA... > > > > It doesn't. 34-bit is PA, 32-bit is VA. > > Quote from T210 TRM: > > "The SMMU is a centralized virtual-to-physical translation for MSS. It > maps a 32-bit virtual address to a 34-bit physical address. If the > client address is 40 bits then bits 39:32 are ignored." If you scroll down by a couple of sections, you can see 34-bit virtual addresses in section 18.6.1.2; and if checking one ASID register, you can see it mention the extra two bits va[33:32]. However, the driver currently sets its geometry.aperture_end to 32-bit, and we can only get 32-bit IOVAs using PDE and PTE only, so I think it should be safe to remove the castings here. I'll wait for a couple of days and see if there'd be other comments for me to address in next version. > Even if it supported more than 32bit, then the returned ulong is 32bit, > which doesn't make sense. On ARM64 (Tegra210), isn't ulong 64-bit?