From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C48EDC433F5 for ; Fri, 1 Oct 2021 22:45:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD65961ADF for ; Fri, 1 Oct 2021 22:45:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356147AbhJAWri (ORCPT ); Fri, 1 Oct 2021 18:47:38 -0400 Received: from mga17.intel.com ([192.55.52.151]:38097 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356221AbhJAWrI (ORCPT ); Fri, 1 Oct 2021 18:47:08 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10124"; a="205756670" X-IronPort-AV: E=Sophos;i="5.85,340,1624345200"; d="scan'208";a="205756670" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2021 15:44:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,340,1624345200"; d="scan'208";a="565344018" Received: from chang-linux-3.sc.intel.com ([172.25.66.175]) by fmsmga002.fm.intel.com with ESMTP; 01 Oct 2021 15:44:19 -0700 From: "Chang S. Bae" To: bp@suse.de, luto@kernel.org, tglx@linutronix.de, mingo@kernel.org, x86@kernel.org Cc: len.brown@intel.com, lenb@kernel.org, dave.hansen@intel.com, thiago.macieira@intel.com, jing2.liu@intel.com, ravi.v.shankar@intel.com, linux-kernel@vger.kernel.org, chang.seok.bae@intel.com Subject: [PATCH v11 22/29] x86/fpu/amx: Enable the AMX feature in 64-bit mode Date: Fri, 1 Oct 2021 15:37:21 -0700 Message-Id: <20211001223728.9309-23-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001223728.9309-1-chang.seok.bae@intel.com> References: <20211001223728.9309-1-chang.seok.bae@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In 64-bit mode, include the AMX state components in XFEATURE_MASK_USER_SUPPORTED. Signed-off-by: Chang S. Bae Reviewed-by: Len Brown Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org --- Changes from v5: * Adjusted macro changes and moved the disabling code for non-64-bit mode for the new base changes. Changes from v4: * Removed the irrelevant line from the changelog. (Thomas Gleixner) --- arch/x86/include/asm/fpu/xstate.h | 3 ++- arch/x86/kernel/fpu/xstate.c | 6 +++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/xstate.h index 0e355dfe711b..0b337e913423 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -37,7 +37,8 @@ XFEATURE_MASK_Hi16_ZMM | \ XFEATURE_MASK_PKRU | \ XFEATURE_MASK_BNDREGS | \ - XFEATURE_MASK_BNDCSR) + XFEATURE_MASK_BNDCSR | \ + XFEATURE_MASK_XTILE) /* Require ARCH_SET_STATE_ENABLE from XTILE_CFG and later states */ #define XFEATURE_MASK_PERMISSION_REQUIRED GENMASK_ULL(63, XFEATURE_XTILE_CFG) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 2ebc98c4b496..43539893dd82 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -492,7 +492,8 @@ static void __init print_xstate_offset_size(void) XFEATURE_MASK_PKRU | \ XFEATURE_MASK_BNDREGS | \ XFEATURE_MASK_BNDCSR | \ - XFEATURE_MASK_PASID) + XFEATURE_MASK_PASID | \ + XFEATURE_MASK_XTILE) /* * setup the xstate image representing the init state @@ -1008,6 +1009,9 @@ void __init fpu__init_system_xstate(void) xfeatures_mask_all &= XFEATURE_MASK_USER_SUPPORTED | XFEATURE_MASK_SUPERVISOR_SUPPORTED; + if (!IS_ENABLED(CONFIG_X86_64)) + xfeatures_mask_all &= ~XFEATURE_MASK_XTILE; + /* Store it for paranoia check at the end */ xfeatures = xfeatures_mask_all; -- 2.17.1