From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3607C433EF for ; Mon, 4 Oct 2021 15:40:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C9C0461354 for ; Mon, 4 Oct 2021 15:40:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235797AbhJDPmn convert rfc822-to-8bit (ORCPT ); Mon, 4 Oct 2021 11:42:43 -0400 Received: from relay9-d.mail.gandi.net ([217.70.183.199]:44033 "EHLO relay9-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234207AbhJDPmm (ORCPT ); Mon, 4 Oct 2021 11:42:42 -0400 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay9-d.mail.gandi.net (Postfix) with ESMTPSA id F40E9FF818; Mon, 4 Oct 2021 15:40:49 +0000 (UTC) Date: Mon, 4 Oct 2021 17:40:48 +0200 From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus Cc: , , stable@vger.kernel.org, Jan Hoffmann , Kestrel seventyfour Subject: Re: [PATCH 9/9] mtd: rawnand: xway: Keep the driver compatible with on-die ECC engines Message-ID: <20211004174048.608b07ef@xps13> In-Reply-To: <20210928222258.199726-10-miquel.raynal@bootlin.com> References: <20210928222258.199726-1-miquel.raynal@bootlin.com> <20210928222258.199726-10-miquel.raynal@bootlin.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jan, miquel.raynal@bootlin.com wrote on Wed, 29 Sep 2021 00:22:48 +0200: > Following the introduction of the generic ECC engine infrastructure, it > was necessary to reorganize the code and move the ECC configuration in > the ->attach_chip() hook. Failing to do that properly lead to a first > series of fixes supposed to stabilize the situation. Unfortunately, this > only fixed the use of software ECC engines, preventing any other kind of > engine to be used, including on-die ones. > > It is now time to (finally) fix the situation by ensuring that we still > provide a default (eg. software ECC) but will still support different > ECC engines such as on-die ECC engines if properly described in the > device tree. > > There are no changes needed on the core side in order to do this, but we > just need to leverage the logic there which allows: > 1- a subsystem default (set to Host engines in the raw NAND world) > 2- a driver specific default (here set to software ECC engines) > 3- any type of engine requested by the user (ie. described in the DT) > > As the raw NAND subsystem has not yet been fully converted to the ECC > engine infrastructure, in order to provide a default ECC engine for this > driver we need to set chip->ecc.engine_type *before* calling > nand_scan(). During the initialization step, the core will consider this > entry as the default engine for this driver. This value may of course > be overloaded by the user if the usual DT properties are provided. > > Fixes: d525914b5bd8 ("mtd: rawnand: xway: Move the ECC initialization to ->attach_chip()") > Cc: stable@vger.kernel.org > Cc: Jan Hoffmann I think you already tested this change and validated it, would you mind providing your Tested-by? > Cc: Kestrel seventyfour > Signed-off-by: Miquel Raynal > --- > drivers/mtd/nand/raw/xway_nand.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/mtd/nand/raw/xway_nand.c b/drivers/mtd/nand/raw/xway_nand.c > index 26751976e502..236fd8c5a958 100644 > --- a/drivers/mtd/nand/raw/xway_nand.c > +++ b/drivers/mtd/nand/raw/xway_nand.c > @@ -148,9 +148,8 @@ static void xway_write_buf(struct nand_chip *chip, const u_char *buf, int len) > > static int xway_attach_chip(struct nand_chip *chip) > { > - chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; > - > - if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) > + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && > + chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) > chip->ecc.algo = NAND_ECC_ALGO_HAMMING; > > return 0; > @@ -219,6 +218,13 @@ static int xway_nand_probe(struct platform_device *pdev) > | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P > | cs_flag, EBU_NAND_CON); > > + /* > + * This driver assumes that the default ECC engine should be TYPE_SOFT. > + * Set ->engine_type before registering the NAND devices in order to > + * provide a driver specific default value. > + */ > + data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; > + > /* Scan to find existence of the device */ > err = nand_scan(&data->chip, 1); > if (err) Thanks, Miquèl