From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A7C3C433F5 for ; Mon, 11 Oct 2021 13:25:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4025960E8B for ; Mon, 11 Oct 2021 13:25:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236902AbhJKN07 (ORCPT ); Mon, 11 Oct 2021 09:26:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:53772 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236854AbhJKN05 (ORCPT ); Mon, 11 Oct 2021 09:26:57 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9F9E460F35; Mon, 11 Oct 2021 13:24:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1633958697; bh=LEZbhktiDsSW+AwzStPDh+VwFomRdqomqsmfTAm2/aY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y8cUKprreXse2sf+Od1xtI2PwfWHJEK1o0LhxjXvuXjvtKARsNBuXxxJzowHNZh9I 2AKJ1iEMrNNbky/N5gmhCqdWeesxYR4OzP2LMF7JSTYPVy2oqSjx92arAgil2QBZTX b+4UFaSi207sdMjcsVAvxcTZOEv4/QLC8kM/+T0oJqjPr14yCryQgQpx8e0JpHS+oc QjW5U2Tnrd9MOwGz4/8RvcpncnjpOEmGsBwVDR/K4CrfiuwhhVHCJGuWhsslCEI6dY t0zaEzkhF5lHCU3PUpJ4DFtHfwxb+oBeQnYk1xb+BYfDBY1xkFDxDRY26EvwLPjb21 jHM2gP0IQZRgw== From: guoren@kernel.org To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Rob Herring , Palmer Dabbelt Subject: [PATCH 2/2] dt-bindings: update riscv plic claim-mask-support property Date: Mon, 11 Oct 2021 21:24:31 +0800 Message-Id: <20211011132431.2792797-2-guoren@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211011132431.2792797-1-guoren@kernel.org> References: <20211011132431.2792797-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren Add claim-mask-support to control riscv,plic don't call unnecessary mask/unmask operations. Signed-off-by: Guo Ren Cc: Rob Herring Cc: Palmer Dabbelt Cc: Anup Patel Cc: Atish Patra --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 08d5a57ce00f..f32c1792604c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -71,6 +71,8 @@ properties: description: Specifies how many external interrupts are supported by this controller. + claim-mask-support: true + required: - compatible - '#address-cells' -- 2.25.1