[PATCH v2 10/14] mtd: spinand: Add support for Power-on-Reset (PoR) instruction

Apurva Nandan
2021-10-11T20:47:35Z

Manufacturers like Gigadevice and Winbond are adding Power-on-Reset
functionality in their SPI NAND flash chips. PoR instruction consists
of a 66h command followed by 99h command, and is different from the FFh
reset. The reset command FFh just clears the status only registers,
while the PoR command erases all the configurations written to the
flash and is equivalent to a power-down -> power-up cycle.

Add support for the Power-on-Reset command for any flash that provides
this feature.

Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf

Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
drivers/mtd/nand/spi/core.c | 43 +++++++++++++++++++++++++++++++++++++
include/linux/mtd/spinand.h | 17 +++++++++++++++
2 files changed, 60 insertions(+)

diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 2bea21bd9747..9b570570ee81 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -9,6 +9,7 @@

#define pr_fmt(fmt) "spi-nand: " fmt

+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
@@ -668,6 +669,48 @@ static int spinand_reset_op(struct spinand_device *spinand)
NULL);
}

+static int spinand_power_on_rst_op(struct spinand_device *spinand)
+{
+ struct spi_mem_op op;
+ int ret;
+
+ if (!(spinand->flags & SPINAND_HAS_POR_CMD_BIT))
+ return -EOPNOTSUPP;
+
+ /*
+ * If flash is in a busy state, wait for it to finish the operation.
+ * As the operation is unknown, use reset poll delays here.
+ */
+ ret = spinand_wait(spinand,
+ SPINAND_RESET_INITIAL_DELAY_US,
+ SPINAND_RESET_POLL_DELAY_US,
+ NULL);
+ if (ret)
+ return ret;
+
+ op = (struct spi_mem_op)SPINAND_EN_POWER_ON_RST_OP;
+
+ spinand_patch_op(spinand, &op);
+ ret = spi_mem_exec_op(spinand->spimem, &op);
+ if (ret)
+ return ret;
+
+ op = (struct spi_mem_op)SPINAND_POWER_ON_RST_OP;
+
+ spinand_patch_op(spinand, &op);
+ ret = spi_mem_exec_op(spinand->spimem, &op);
+ if (ret)
+ return ret;
+
+ /* PoR can take max 500 us to complete, so sleep for 600 to 700 us*/
+ usleep_range(SPINAND_POR_MIN_DELAY_US, SPINAND_POR_MAX_DELAY_US);
+
+ dev_dbg(&spinand->spimem->spi->dev,
+ "%s SPI NAND reset to Power-On-Reset state.\n",
+ spinand->manufacturer->name);
+ return 0;
+}
+
static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
{
return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 21a4e5adcd59..baaf8e94f301 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -26,6 +26,18 @@
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_NO_DATA)

+#define SPINAND_EN_POWER_ON_RST_OP \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x66, 1), \
+ SPI_MEM_OP_NO_ADDR, \
+ SPI_MEM_OP_NO_DUMMY, \
+ SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_POWER_ON_RST_OP \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x99, 1), \
+ SPI_MEM_OP_NO_ADDR, \
+ SPI_MEM_OP_NO_DUMMY, \
+ SPI_MEM_OP_NO_DATA)
+
#define SPINAND_WR_EN_DIS_OP(enable) \
SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
SPI_MEM_OP_NO_ADDR, \
@@ -218,6 +230,8 @@ struct spinand_device;
* reading/programming/erasing when the RESET occurs. Since we always
* issue a RESET when the device is IDLE, 5us is selected for both initial
* and poll delay.
+ * Power on Reset can take upto 500 us to complete, so sleep for 600 us
+ * to 700 us safely.
*/
#define SPINAND_READ_INITIAL_DELAY_US 6
#define SPINAND_READ_POLL_DELAY_US 5
@@ -227,6 +241,8 @@ struct spinand_device;
#define SPINAND_WRITE_POLL_DELAY_US 15
#define SPINAND_ERASE_INITIAL_DELAY_US 250
#define SPINAND_ERASE_POLL_DELAY_US 50
+#define SPINAND_POR_MIN_DELAY_US 600
+#define SPINAND_POR_MAX_DELAY_US 700

#define SPINAND_WAITRDY_TIMEOUT_MS 400

@@ -351,6 +367,7 @@ struct spinand_ecc_info {
#define SPINAND_HAS_QE_BIT BIT(0)
#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
#define SPINAND_HAS_OCTAL_DTR_BIT BIT(2)
+#define SPINAND_HAS_POR_CMD_BIT BIT(3)

/**
* struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
--
2.25.1