From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Guo Ren <guoren@linux.alibaba.com>, Rob Herring <robh@kernel.org>,
Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PATCH V2 1/2] dt-bindings: update riscv plic compatible string
Date: Tue, 12 Oct 2021 23:34:31 +0800 [thread overview]
Message-ID: <20211012153432.2817285-1-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
Add the compatible string "thead,c9xx-plic" to the riscv plic
bindings to support SOCs with thead,c9xx processor cores.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@wdc.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 08d5a57ce00f..202eb7666f9b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -46,6 +46,7 @@ properties:
- enum:
- sifive,fu540-c000-plic
- canaan,k210-plic
+ - thead,c9xx-plic
- const: sifive,plic-1.0.0
reg:
--
2.25.1
next reply other threads:[~2021-10-12 15:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-12 15:34 guoren [this message]
2021-10-12 15:34 ` [PATCH V2 2/2] irqchip/sifive-plic: Add thead,c9xx-plic support guoren
2021-10-12 16:40 ` Anup Patel
2021-10-12 23:06 ` Heiko Stübner
2021-10-13 0:47 ` Guo Ren
2021-10-13 0:48 ` Guo Ren
2021-10-12 15:41 ` [PATCH V2 1/2] dt-bindings: update riscv plic compatible string Heiko Stübner
2021-10-13 0:41 ` Guo Ren
2021-10-12 18:28 ` Atish Patra
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