From: Bharat Bhushan <bbhushan2@marvell.com>
To: <will@kernel.org>, <mark.rutland@arm.com>, <robh+dt@kernel.org>,
<bbudiredla@marvell.com>, <sgoutham@marvell.com>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Bharat Bhushan <bbhushan2@marvell.com>
Subject: [PATCH v5 0/4] cn10k DDR Performance monitor support
Date: Mon, 18 Oct 2021 09:50:11 +0530 [thread overview]
Message-ID: <20211018042015.25151-1-bbhushan2@marvell.com> (raw)
This patch series adds DDR performance monitor support
on Marvell cn10k series of processor.
First patch adds device tree binding changes.
Second patch add basic support (without overflow and event
ownership). Third and fourth patch adds overflow and event
ownership respectively.
Seems like 4th patch can be merged in second patch,
For easy review it is currently separate
v4->v5:
- Added missing COMPILE_TEST dependency
v3->v4:
- Added Rob Herring reviewed-by for dt-binding patch
v2->v3:
- dt-binding, ddrcpmu@1 -> pmu@87e1c0000000
- Add COMPILE_TEST as a dependency
- Switch to sysfs_emit()
- Error propagation when invalif event requested
- Switch to devm_platform_get_and_ioremap_resource()
- Other review comments on v2.
v1->v2:
- DT binding changed to new DT Schema
- writeq/readq changed to respective relaxed
- Using PMU_EVENT_ATTR_ID
Bharat Bhushan (4):
dt-bindings: perf: marvell: cn10k ddr performance monitor
perf/marvell: CN10k DDR performance monitor support
perf/marvell: cn10k DDR perfmon event overflow handling
perf/marvell: cn10k DDR perf event core ownership
.../bindings/perf/marvell-cn10k-ddr.yaml | 37 +
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile | 1 +
drivers/perf/marvell_cn10k_ddr_pmu.c | 756 ++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
5 files changed, 802 insertions(+)
create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
create mode 100644 drivers/perf/marvell_cn10k_ddr_pmu.c
--
2.17.1
next reply other threads:[~2021-10-18 4:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-18 4:20 Bharat Bhushan [this message]
2021-10-18 4:20 ` [PATCH v5 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor Bharat Bhushan
2021-10-18 4:20 ` [PATCH v5 2/4] perf/marvell: CN10k DDR performance monitor support Bharat Bhushan
2021-10-18 4:37 ` Bhaskara Budiredla
2021-10-25 5:20 ` kernel test robot
2021-10-25 9:40 ` kernel test robot
2021-10-25 16:37 ` kernel test robot
2021-10-18 4:20 ` [PATCH v5 3/4] perf/marvell: cn10k DDR perfmon event overflow handling Bharat Bhushan
2021-10-18 4:37 ` Bhaskara Budiredla
2021-10-18 4:20 ` [PATCH v5 4/4] perf/marvell: cn10k DDR perf event core ownership Bharat Bhushan
2021-10-18 4:37 ` Bhaskara Budiredla
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211018042015.25151-1-bbhushan2@marvell.com \
--to=bbhushan2@marvell.com \
--cc=bbudiredla@marvell.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=sgoutham@marvell.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox