From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com,
heiko@sntech.de, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Guo Ren <guoren@linux.alibaba.com>
Subject: [PATCH V5 0/3] Add thead,c900-plic support
Date: Sun, 24 Oct 2021 09:33:00 +0800 [thread overview]
Message-ID: <20211024013303.3499461-1-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.
Changes since V5:
- Move back to mask/unmask
- Fixup the problem in eoi callback
- Remove allwinner,sun20i-d1 IRQCHIP_DECLARE
- Rewrite comment log
- Add DT list
- Fixup compatible string
- Remove allwinner-d1 compatible
- make dt_binding_check
- Add T-head vendor-prefixes
Changes since V4:
- Update description in errata style
- Update enum suggested by Anup, Heiko, Samuel
- Update comment by Anup
- Add cover-letter
Changes since V3:
- Rename "c9xx" to "c900"
- Add thead,c900-plic in the description section
- Add sifive_plic_chip and thead_plic_chip for difference
Changes since V2:
- Add a separate compatible string "thead,c9xx-plic"
- set irq_mask/unmask of "plic_chip" to NULL and point
irq_enable/disable of "plic_chip" to plic_irq_mask/unmask
- Add a detailed comment block in plic_init() about the
differences in Claim/Completion process of RISC-V PLIC and C9xx
PLIC.
Guo Ren (3):
dt-bindings: vendor-prefixes: add T-Head Semiconductor
dt-bindings: update riscv plic compatible string
irqchip/sifive-plic: Fixup thead,c900-plic request_threaded_irq with
ONESHOT
.../sifive,plic-1.0.0.yaml | 15 +++++--
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
drivers/irqchip/irq-sifive-plic.c | 44 ++++++++++++++++++-
3 files changed, 56 insertions(+), 5 deletions(-)
--
2.25.1
next reply other threads:[~2021-10-24 1:41 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-24 1:33 guoren [this message]
2021-10-24 1:33 ` [PATCH V5 1/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren
2021-11-02 2:21 ` Guo Ren
2021-11-02 12:59 ` Rob Herring
2021-11-03 1:52 ` Guo Ren
2021-10-24 1:33 ` [PATCH V5 2/3] dt-bindings: update riscv plic compatible string guoren
2021-10-24 7:35 ` Anup Patel
2021-10-24 9:01 ` Guo Ren
2021-10-24 9:18 ` Anup Patel
2021-10-24 9:35 ` Guo Ren
2021-10-24 9:52 ` Anup Patel
2021-10-24 10:04 ` Guo Ren
2021-10-24 1:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic request_threaded_irq with ONESHOT guoren
2021-10-25 10:48 ` Marc Zyngier
2021-10-25 13:33 ` Guo Ren
2021-10-28 10:55 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Nikita Shubin
2021-10-28 14:58 ` Marc Zyngier
2021-10-30 10:27 ` Anup Patel
2021-11-01 2:20 ` Guo Ren
2021-11-01 2:53 ` Anup Patel
2021-11-01 3:57 ` Guo Ren
2021-11-01 4:27 ` Anup Patel
2021-11-01 7:56 ` Guo Ren
2021-11-01 9:27 ` Marc Zyngier
2021-11-01 9:25 ` Marc Zyngier
2021-11-01 2:00 ` Guo Ren
2021-11-01 5:11 ` Vincent Pelletier
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