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[73.25.156.94]) by smtp.gmail.com with ESMTPSA id d10sm3131569pfd.21.2021.11.03.13.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 13:59:08 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/2] drm/msm/gpu: Respect PM QoS constraints Date: Wed, 3 Nov 2021 14:04:02 -0700 Message-Id: <20211103210402.623099-2-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211103210402.623099-1-robdclark@gmail.com> References: <20211103210402.623099-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rob Clark Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 31 +++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index b24e5475cafb..427c55002f4d 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -158,6 +158,33 @@ void msm_devfreq_suspend(struct msm_gpu *gpu) devfreq_suspend_device(gpu->devfreq.devfreq); } +static void set_target(struct msm_gpu *gpu, unsigned long freq) +{ + struct msm_gpu_devfreq *df = &gpu->devfreq; + unsigned long min_freq, max_freq; + u32 flags = 0; + + /* + * When setting the target freq internally, we need to apply PM QoS + * constraints (such as cooling): + */ + min_freq = dev_pm_qos_read_value(df->devfreq->dev.parent, + DEV_PM_QOS_MIN_FREQUENCY); + max_freq = dev_pm_qos_read_value(df->devfreq->dev.parent, + DEV_PM_QOS_MAX_FREQUENCY); + + if (freq < min_freq) { + freq = min_freq; + flags &= ~DEVFREQ_FLAG_LEAST_UPPER_BOUND; /* Use GLB */ + } + if (freq > max_freq) { + freq = max_freq; + flags |= DEVFREQ_FLAG_LEAST_UPPER_BOUND; /* Use LUB */ + } + + msm_devfreq_target(&gpu->pdev->dev, &freq, flags); +} + void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor) { struct msm_gpu_devfreq *df = &gpu->devfreq; @@ -173,7 +200,7 @@ void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor) freq *= factor; - msm_devfreq_target(&gpu->pdev->dev, &freq, 0); + set_target(gpu, freq); mutex_unlock(&df->devfreq->lock); } @@ -212,7 +239,7 @@ void msm_devfreq_active(struct msm_gpu *gpu) df->idle_freq = 0; - msm_devfreq_target(&gpu->pdev->dev, &target_freq, 0); + set_target(gpu, target_freq); /* * Reset the polling interval so we aren't inconsistent -- 2.31.1