[PATCH] mmc: sdhci-tegra: Add support to enumerate in HS400ES mode

[Prathamesh Shete <pshete@nvidia.com>]

When CMD13 is sent after switching to HS400 mode, the bus
is operating at either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
To meet Tegra SDHCI requirement at HS400 mode, force SDHCI
interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
controller CAR clock and the interface clock are rate matched.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
 drivers/mmc/host/sdhci-tegra.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 387ce9cdbd7c..d800396d1112 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -123,6 +123,8 @@
 					 SDHCI_TRNS_BLK_CNT_EN | \
 					 SDHCI_TRNS_DMA)
 
+static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
+
 struct sdhci_tegra_soc_data {
 	const struct sdhci_pltfm_data *pdata;
 	u64 dma_mask;
@@ -369,6 +371,16 @@ static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
 
 	sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
 
+	/*
+	 * When CMD13 is sent after switching to HS400 mode, the bus
+	 * is operating at either MMC_HIGH_26_MAX_DTR or
+	 * MMC_HIGH_52_MAX_DTR.
+	 * To meet Tegra SDHCI requirement at HS400 mode, force SDHCI
+	 * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
+	 * controller CAR clock and the interface clock are rate matched.
+	 */
+	tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR);
+
 }
 
 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
-- 
2.17.1