From: Jisheng Zhang <jszhang@kernel.org>
To: Anup Patel <anup@brainfault.org>
Cc: "Wei Fu" <wefu@redhat.com>, "Anup Patel" <anup.patel@wdc.com>,
"atish patra" <atishp04@gmail.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Guo Ren" <guoren@kernel.org>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Christoph Hellwig" <hch@lst.de>,
"Liu Shaohua" <liush@allwinnertech.com>,
"Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
taiten.peng@canonical.com,
"Aniket Ponkshe" <aniket.ponkshe@canonical.com>,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
"Gordan Markus" <gordan.markus@canonical.com>,
"Guo Ren" <guoren@linux.alibaba.com>,
"Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>,
"Maxime Ripard" <maxime@cerno.tech>,
"Daniel Lustig" <dlustig@nvidia.com>,
"Greg Favor" <gfavor@ventanamicro.com>,
"Andrea Mondelli" <andrea.mondelli@huawei.com>,
"Jonathan Behrens" <behrensj@mit.edu>,
Xinhaoqu <xinhaoqu@huawei.com>,
"Bill Huffman" <huffman@cadence.com>,
"Nick Kossifidis" <mick@ics.forth.gr>,
"Allen Baum" <allen.baum@esperantotech.com>,
"Josh Scheid" <jscheid@ventanamicro.com>,
"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [PATCH V4 2/2] riscv: add RISC-V Svpbmt extension supports
Date: Wed, 1 Dec 2021 21:29:48 +0800 [thread overview]
Message-ID: <20211201133758.5771EC53FCC@smtp.kernel.org> (raw)
In-Reply-To: <CAAhSdy1LF4Km8ax00NdT3sUYqJRaW-nwXFCpviahpcDj2LLUAw@mail.gmail.com>
On Wed, 1 Dec 2021 11:48:44 +0530
Anup Patel <anup@brainfault.org> wrote:
> > > > */
> > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > > index d959d207a40d..fa7480cb8b87 100644
> > > > --- a/arch/riscv/kernel/cpufeature.c
> > > > +++ b/arch/riscv/kernel/cpufeature.c
> > > > @@ -8,6 +8,7 @@
> > > >
> > > > #include <linux/bitmap.h>
> > > > #include <linux/of.h>
> > > > +#include <linux/pgtable.h>
> > > > #include <asm/processor.h>
> > > > #include <asm/hwcap.h>
> > > > #include <asm/smp.h>
> > > > @@ -59,6 +60,38 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
> > > > }
> > > > EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
> > > >
> > > > +static void __init mmu_supports_svpbmt(void)
> > > > +{
> > > > +#if defined(CONFIG_MMU) && defined(CONFIG_64BIT)
> > >
> > > IIRC, Christoph suggested a CONFIG_RISCV_SVPBMT when reviewing v3. What
> > > about that idea?
> >
> > Yes, sorry for missing it, yes, I think we can have something like this
> >
> > config ARCH_HAS_RISCV_SVPBMT
> > bool
> > default n
> >
> > any platform which needs this support, can just
> >
> > select ARCH_HAS_RISCV_SVPBMT
> >
> > and which is the best name? ARCH_HAS_RISCV_SVPBMT or just ARCH_HAS_SVPBMT ?
> >
> > >
> > > > + struct device_node *node;
> > > > + const char *str;
> > > > +
> > > > + for_each_of_cpu_node(node) {
> > > > + if (of_property_read_string(node, "mmu-type", &str))
> > > > + continue;
> > > > +
> > > > + if (!strncmp(str + 6, "none", 4))
> > > > + continue;
> > > > +
> > > > + if (of_property_read_string(node, "mmu", &str))
> > > > + continue;
> > > > +
> > > > + if (strncmp(str + 6, "svpmbt", 6))
> > > > + continue;
> > > > + }
> > > > +
> > > > + __svpbmt.pma = _SVPBMT_PMA;
> > > > + __svpbmt.nocache = _SVPBMT_NC;
> > > > + __svpbmt.io = _SVPBMT_IO;
> > > > + __svpbmt.mask = _SVPBMT_MASK;
> > > > +#endif
> > > > +}
> > > > +
> > > > +static void __init mmu_supports(void)
> > >
> > > can we remove this function currently? Instead, directly call
> > > mmu_supports_svpbmt()?
> > >
> > > > +{
> > > > + mmu_supports_svpbmt();
> > > > +}
> > > > +
> > > > void __init riscv_fill_hwcap(void)
> > > > {
> > > > struct device_node *node;
> > > > @@ -67,6 +100,8 @@ void __init riscv_fill_hwcap(void)
> > > > size_t i, j, isa_len;
> > > > static unsigned long isa2hwcap[256] = {0};
> > > >
> > > > + mmu_supports();
> > > > +
> > > > isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
> > > > isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
> > > > isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A;
> > > > diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> > > > index 24b2b8044602..e4e658165ee1 100644
> > > > --- a/arch/riscv/mm/init.c
> > > > +++ b/arch/riscv/mm/init.c
> > > > @@ -854,3 +854,8 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node,
> > > > return vmemmap_populate_basepages(start, end, node, NULL);
> > > > }
> > > > #endif
> > > > +
> > > > +#if defined(CONFIG_64BIT)
> > > > +struct __svpbmt_struct __svpbmt __ro_after_init;
> > >
> > > Added the structure for all RV64 including NOMMU case and those platforms
> > > which doen't want SVPBMT at all, I believe Christoph's CONFIG_RISCV_SVPBMT
> > > suggestion can solve this problem.
> >
> > see ARCH_HAS_RISCV_SVPBMT above . :-)
>
> This config option will not align with the goal of having a unified
> kernel image which works on HW with/without Svpmbt.
Just my thoughts:
If disable this option, HW without Svpbmt can work as before; Hw with
Svpbmt will only have a basic working, those DMA etc can't work.
If enable this option, HW without Svpbmt can work as well, but with
a bit overhead and waste. HW with Svpbmt can work. So this option gives
those platforms which doesn't need Svpbmt a chance to totally disable it.
But linux distributions which want a uniified Image usually enable features as
much as possible, so IMHO, this config option can still meet unified kernel
image requirement.
>
> Better to explore code patching approaches which have zero
> overhead.
It would be nice if the Svpbmt can be supported via. coding patching tech.
Thanks
next prev parent reply other threads:[~2021-12-01 13:38 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-29 1:40 [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports wefu
2021-11-29 1:40 ` [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt wefu
2021-11-29 8:54 ` Heinrich Schuchardt
2021-11-29 12:06 ` Heiko Stübner
2021-11-30 12:07 ` Heiko Stübner
2021-11-30 13:17 ` Jessica Clarke
2021-11-30 13:27 ` Heiko Stübner
2021-11-30 13:59 ` Jessica Clarke
2021-11-30 15:01 ` Philipp Tomsich
2021-11-30 16:12 ` Jessica Clarke
2021-12-01 1:21 ` Atish Patra
2021-12-01 3:06 ` Tsukasa OI
2021-12-01 8:15 ` Atish Patra
2021-12-01 8:30 ` Heiko Stübner
[not found] ` <CAELrHRDb9oeu_FokyhUFQ+Yu27=4xqvPdz4=08MXQzh3Bj2Myw@mail.gmail.com>
2021-12-01 10:20 ` Heiko Stübner
2021-12-01 11:05 ` Philipp Tomsich
2021-12-01 13:39 ` Jessica Clarke
2021-12-02 1:31 ` Tsukasa OI
2021-12-02 1:55 ` Atish Patra
2021-12-01 13:28 ` Heiko Stübner
2021-12-02 1:59 ` Atish Patra
2021-11-30 18:45 ` Heiko Stübner
2021-12-01 2:58 ` Wei Fu
2021-11-29 1:40 ` [PATCH V4 2/2] riscv: add RISC-V Svpbmt extension supports wefu
2021-11-29 10:48 ` Alexandre Ghiti
2021-11-29 13:36 ` Jisheng Zhang
2021-12-01 5:05 ` Wei Fu
2021-12-01 6:18 ` Anup Patel
2021-12-01 13:29 ` Jisheng Zhang [this message]
2021-12-03 9:12 ` Wei Fu
2021-11-30 10:18 ` Guo Ren
2021-12-01 3:03 ` Wei Fu
2021-11-30 18:46 ` Heiko Stübner
2021-12-01 3:00 ` Wei Fu
2021-11-29 13:33 ` [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Jisheng Zhang
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