[GIT PULL] irqchip fixes for 5.16, take #2

[Marc Zyngier <maz@kernel.org>]

Thomas,

Here's another set of irqchip fixes for 5.16. The main ones are the
MSI allocation fixes for an old Marvell system, another for the Aspeed
SCU driver acking interrupts the wrong way, and one for the ARM NVIC
having the wrong offset of one of the registers.

Please pull,

	M.

The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:

  Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-fixes-5.16-2

for you to fetch changes up to c5e0cbe2858d278a27d5b3fe31890aea5be064c4:

  irqchip: nvic: Fix offset for Interrupt Priority Offsets (2021-12-02 09:27:06 +0000)

----------------------------------------------------------------
irqchip fixes for Linux 5.16, take #2

- Fix Armada-370-XP Multi-MSi allocation to be aligned on the allocation
  size, as required by the PCI spec

- Fix aspeed-scu interrupt acknowledgement by directly writing to the
  register instead of a read-modify-write sequence

- Use standard bitfirl helpers in the MIPS GIC driver instead of custom
  constructs

- Fix the NVIC driver IPR register offset

----------------------------------------------------------------
Billy Tsai (1):
      irqchip/aspeed-scu: Replace update_bits with write_bits.

Geert Uytterhoeven (1):
      irqchip/mips-gic: Use bitfield helpers

Pali Rohár (2):
      irqchip/armada-370-xp: Fix return value of armada_370_xp_msi_alloc()
      irqchip/armada-370-xp: Fix support for Multi-MSI interrupts

Vladimir Murzin (1):
      irqchip: nvic: Fix offset for Interrupt Priority Offsets

 drivers/irqchip/irq-armada-370-xp.c | 16 ++++++----------
 drivers/irqchip/irq-aspeed-scu-ic.c |  4 ++--
 drivers/irqchip/irq-mips-gic.c      |  4 ++--
 drivers/irqchip/irq-nvic.c          |  2 +-
 4 files changed, 11 insertions(+), 15 deletions(-)