Re: [PATCHv5 1/4] arm64: io: Use asm-generic high level MMIO accessors

[kernel test robot <lkp@intel.com>]

Hi Sai,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on rostedt-trace/for-next arnd-asm-generic/master arm-perf/for-next/perf v5.16-rc4 next-20211206]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Sai-Prakash-Ranjan/tracing-rwmmio-arm64-Add-support-to-trace-register-reads-writes/20211206-163212
base:   https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
config: arm64-randconfig-r014-20211206 (https://download.01.org/0day-ci/archive/20211206/202112062304.8qIQUQyF-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/0775ecf0f452d6b76b161d009dab52c90270755a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Sai-Prakash-Ranjan/tracing-rwmmio-arm64-Add-support-to-trace-register-reads-writes/20211206-163212
        git checkout 0775ecf0f452d6b76b161d009dab52c90270755a
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/meson/meson_viu.c:16:
   drivers/gpu/drm/meson/meson_viu.c: In function 'meson_viu_init':
>> drivers/gpu/drm/meson/meson_registers.h:1826:55: warning: conversion from 'long unsigned int' to 'u32' {aka 'unsigned int'} changes value from '18446744071814774785' to '2400190465' [-Woverflow]
    1826 | #define         VIU_OSD_BLEND_REORDER(dest, src)      ((src) << (dest * 4))
         |                                                       ^
   drivers/gpu/drm/meson/meson_viu.c:472:32: note: in expansion of macro 'VIU_OSD_BLEND_REORDER'
     472 |                 writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
         |                                ^~~~~~~~~~~~~~~~~~~~~


vim +1826 drivers/gpu/drm/meson/meson_registers.h

b93a66faeea9ddf Neil Armstrong 2019-03-25  1824  
b93a66faeea9ddf Neil Armstrong 2019-03-25  1825  #define VIU_OSD_BLEND_CTRL 0x39b0
147ae1cbaa18429 Julien Masson  2019-06-24 @1826  #define		VIU_OSD_BLEND_REORDER(dest, src)      ((src) << (dest * 4))
147ae1cbaa18429 Julien Masson  2019-06-24  1827  #define		VIU_OSD_BLEND_DIN_EN(bits)            ((bits & 0xf) << 20)
147ae1cbaa18429 Julien Masson  2019-06-24  1828  #define		VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1   BIT(24)
147ae1cbaa18429 Julien Masson  2019-06-24  1829  #define		VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2  BIT(25)
147ae1cbaa18429 Julien Masson  2019-06-24  1830  #define		VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0    BIT(26)
147ae1cbaa18429 Julien Masson  2019-06-24  1831  #define		VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27)
147ae1cbaa18429 Julien Masson  2019-06-24  1832  #define		VIU_OSD_BLEND_HOLD_LINES(lines)       ((lines & 0x7) << 29)
b93a66faeea9ddf Neil Armstrong 2019-03-25  1833  #define VIU_OSD_BLEND_CTRL1 0x39c0
b93a66faeea9ddf Neil Armstrong 2019-03-25  1834  #define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1
b93a66faeea9ddf Neil Armstrong 2019-03-25  1835  #define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2
b93a66faeea9ddf Neil Armstrong 2019-03-25  1836  #define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3
b93a66faeea9ddf Neil Armstrong 2019-03-25  1837  #define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4
b93a66faeea9ddf Neil Armstrong 2019-03-25  1838  #define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5
b93a66faeea9ddf Neil Armstrong 2019-03-25  1839  #define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6
b93a66faeea9ddf Neil Armstrong 2019-03-25  1840  #define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7
b93a66faeea9ddf Neil Armstrong 2019-03-25  1841  #define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8
b93a66faeea9ddf Neil Armstrong 2019-03-25  1842  #define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9
b93a66faeea9ddf Neil Armstrong 2019-03-25  1843  #define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba
b93a66faeea9ddf Neil Armstrong 2019-03-25  1844  #define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb
b93a66faeea9ddf Neil Armstrong 2019-03-25  1845  #define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc
b93a66faeea9ddf Neil Armstrong 2019-03-25  1846  #define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf
b93a66faeea9ddf Neil Armstrong 2019-03-25  1847  

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0-DAY CI Kernel Test Service, Intel Corporation
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