From: Bjorn Helgaas <helgaas@kernel.org>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Jiri Slaby <jirislaby@kernel.org>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v1 1/1] pci_ids: Keep Intel PCI IDs sorted by value
Date: Sat, 11 Dec 2021 11:35:30 -0600 [thread overview]
Message-ID: <20211211173530.GA397083@bhelgaas> (raw)
In-Reply-To: <20211209195231.2785-1-andriy.shevchenko@linux.intel.com>
On Thu, Dec 09, 2021 at 09:52:31PM +0200, Andy Shevchenko wrote:
> Keep Intel PCI IDs sorted by value.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Applied to pci/misc for v5.17, thanks!
There were a few Intel IDs that used upper-case hex; I lower-cased
them to match the rest.
> ---
> include/linux/pci_ids.h | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 86678588d191..306201cb9aff 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -2738,12 +2738,6 @@
> #define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db
> #define PCI_DEVICE_ID_INTEL_82801EB_12 0x24dc
> #define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd
> -#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1
> -#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2
> -#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
> -#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
> -#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
> -#define PCI_DEVICE_ID_INTEL_ESB_10 0x25ac
> #define PCI_DEVICE_ID_INTEL_82820_HB 0x2500
> #define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501
> #define PCI_DEVICE_ID_INTEL_82850_HB 0x2530
> @@ -2758,14 +2752,15 @@
> #define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582
> #define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590
> #define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592
> +#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1
> +#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2
> +#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
> +#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
> +#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
> +#define PCI_DEVICE_ID_INTEL_ESB_10 0x25ac
> #define PCI_DEVICE_ID_INTEL_5000_ERR 0x25F0
> #define PCI_DEVICE_ID_INTEL_5000_FBD0 0x25F5
> #define PCI_DEVICE_ID_INTEL_5000_FBD1 0x25F6
> -#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770
> -#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772
> -#define PCI_DEVICE_ID_INTEL_3000_HB 0x2778
> -#define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0
> -#define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2
> #define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640
> #define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641
> #define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642
> @@ -2777,6 +2772,11 @@
> #define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
> #define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b
> #define PCI_DEVICE_ID_INTEL_ESB2_18 0x269e
> +#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770
> +#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772
> +#define PCI_DEVICE_ID_INTEL_3000_HB 0x2778
> +#define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0
> +#define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2
> #define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8
> #define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9
> #define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0
> @@ -2941,16 +2941,16 @@
> #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
> #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
> #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
> -#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
> -#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3
> -#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
> -#define PCI_DEVICE_ID_INTEL_5100_22 0x65f6
> #define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030
> #define PCI_DEVICE_ID_INTEL_5400_FBD0 0x4035
> #define PCI_DEVICE_ID_INTEL_5400_FBD1 0x4036
> -#define PCI_DEVICE_ID_INTEL_IOAT_SCNB 0x65ff
> #define PCI_DEVICE_ID_INTEL_EP80579_0 0x5031
> #define PCI_DEVICE_ID_INTEL_EP80579_1 0x5032
> +#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
> +#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3
> +#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
> +#define PCI_DEVICE_ID_INTEL_5100_22 0x65f6
> +#define PCI_DEVICE_ID_INTEL_IOAT_SCNB 0x65ff
> #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
> #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
> #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
> --
> 2.33.0
>
prev parent reply other threads:[~2021-12-11 17:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-09 19:52 [PATCH v1 1/1] pci_ids: Keep Intel PCI IDs sorted by value Andy Shevchenko
2021-12-09 19:56 ` Krzysztof Wilczyński
2021-12-11 17:35 ` Bjorn Helgaas [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211211173530.GA397083@bhelgaas \
--to=helgaas@kernel.org \
--cc=andriy.shevchenko@linux.intel.com \
--cc=bhelgaas@google.com \
--cc=jirislaby@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox