From: Steven Lee <steven_lee@aspeedtech.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Joel Stanley <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"moderated list:ARM/ASPEED MACHINE SUPPORT"
<linux-arm-kernel@lists.infradead.org>,
"moderated list:ARM/ASPEED MACHINE SUPPORT"
<linux-aspeed@lists.ozlabs.org>,
open list <linux-kernel@vger.kernel.org>
Cc: <steven_lee@aspeedtech.com>, <Hongweiz@ami.com>,
<ryan_chen@aspeedtech.com>, <billy_tsai@aspeedtech.com>
Subject: [PATCH v1 0/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq
Date: Tue, 14 Dec 2021 12:02:37 +0800 [thread overview]
Message-ID: <20211214040239.8977-1-steven_lee@aspeedtech.com> (raw)
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins)
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.
This patch series contains a patch for fixing wrong hwirq base in
irq handler.
Please help to review.
Steven Lee (1):
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.17.1
next reply other threads:[~2021-12-14 4:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-14 4:02 Steven Lee [this message]
2021-12-14 4:02 ` [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler Steven Lee
2021-12-22 9:18 ` Bartosz Golaszewski
2022-01-03 9:50 ` Bartosz Golaszewski
2022-01-12 0:53 ` Joel Stanley
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