From: Rob Herring <robh@kernel.org>
To: Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH] arm64: dts: imx8qm: Drop CPU 'arm,armv8' compatible
Date: Fri, 17 Dec 2021 11:39:08 -0600 [thread overview]
Message-ID: <20211217173908.3201517-1-robh@kernel.org> (raw)
The CPU 'arm,armv8' compatible is only for s/w models, so remove it from
i.MX8QM CPU nodes.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
Note that the PMU node is also wrong as it should have separate A72 and
A53 nodes to get uarch specific events, but that needs some GIC changes.
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index aebbe2b84aa1..b13f09ca0404 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -54,7 +54,7 @@ core1 {
A53_0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
@@ -62,7 +62,7 @@ A53_0: cpu@0 {
A53_1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
@@ -70,7 +70,7 @@ A53_1: cpu@1 {
A53_2: cpu@2 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
@@ -78,7 +78,7 @@ A53_2: cpu@2 {
A53_3: cpu@3 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
@@ -86,7 +86,7 @@ A53_3: cpu@3 {
A72_0: cpu@100 {
device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
+ compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&A72_L2>;
@@ -94,7 +94,7 @@ A72_0: cpu@100 {
A72_1: cpu@101 {
device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
+ compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&A72_L2>;
--
2.32.0
next reply other threads:[~2021-12-17 17:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-17 17:39 Rob Herring [this message]
2022-01-24 14:53 ` [PATCH] arm64: dts: imx8qm: Drop CPU 'arm,armv8' compatible Rob Herring
2022-01-26 12:09 ` Shawn Guo
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