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From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Anup Patel <anup@brainfault.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Atish Patra <atishp@atishpatra.org>,
	Damien Le Moal <damien.lemoal@wdc.com>,
	devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>
Subject: [PATCH v3 2/6] RISC-V: Do not print the SBI version during HSM extension boot print
Date: Thu, 20 Jan 2022 01:09:14 -0800	[thread overview]
Message-ID: <20220120090918.2646626-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20220120090918.2646626-1-atishp@rivosinc.com>

The HSM extension information log also prints the SBI version v0.2. This
is misleading as the underlying firmware SBI version may be different
from v0.2.

Remove the unncessary printing of SBI version.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kernel/cpu_ops.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
index 1985884fe829..3f5a38b03044 100644
--- a/arch/riscv/kernel/cpu_ops.c
+++ b/arch/riscv/kernel/cpu_ops.c
@@ -38,7 +38,7 @@ void __init cpu_set_ops(int cpuid)
 #if IS_ENABLED(CONFIG_RISCV_SBI)
 	if (sbi_probe_extension(SBI_EXT_HSM) > 0) {
 		if (!cpuid)
-			pr_info("SBI v0.2 HSM extension detected\n");
+			pr_info("SBI HSM extension detected\n");
 		cpu_ops[cpuid] = &cpu_ops_sbi;
 	} else
 #endif
-- 
2.30.2


  parent reply	other threads:[~2022-01-20  9:10 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-20  9:09 [PATCH v3 0/6] Sparse HART id support Atish Patra
2022-01-20  9:09 ` [PATCH v3 1/6] RISC-V: Avoid using per cpu array for ordered booting Atish Patra
2022-01-20  9:09 ` Atish Patra [this message]
2022-01-20  9:09 ` [PATCH v3 3/6] RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method Atish Patra
2022-01-20  9:09 ` [PATCH v3 5/6] RISC-V: Move spinwait booting method to its own config Atish Patra
2022-01-20  9:09 ` [PATCH v3 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap Atish Patra
2022-01-25 20:12   ` Geert Uytterhoeven
2022-01-25 20:17     ` Atish Patra
2022-01-25 20:52       ` Geert Uytterhoeven
2022-01-25 21:11         ` Ron Economos
2022-01-25 22:26   ` Jessica Clarke
2022-01-25 22:29     ` David Laight
2022-01-26  2:21     ` Atish Patra
2022-01-26  8:28       ` Geert Uytterhoeven
2022-01-26  9:10         ` Geert Uytterhoeven
2022-01-27  1:01           ` Atish Patra
2022-01-27  8:48             ` Geert Uytterhoeven
2022-01-27  8:48               ` Geert Uytterhoeven
2022-01-27 10:03               ` Geert Uytterhoeven
2022-01-27 10:17                 ` Andreas Schwab
     [not found]               ` <CAOnJCU+U0xmw-_yTEUo9ZXO5pvoJ6VCGu+jjU-Sa2MnhcAha6Q@mail.gmail.com>
2022-01-28  8:39                 ` Geert Uytterhoeven
2022-01-28  8:55                   ` Geert Uytterhoeven
2022-01-31 12:09                   ` Anup Patel
2022-01-31 13:27                     ` Geert Uytterhoeven
2022-01-27  9:56             ` Ron Economos
2022-01-31  8:35             ` Anup Patel
2022-01-20 18:17 ` [PATCH v3 0/6] Sparse HART id support Palmer Dabbelt

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