From: James Clark <james.clark@arm.com>
To: suzuki.poulose@arm.com, mathieu.poirier@linaro.org,
coresight@lists.linaro.org
Cc: leo.yan@linaro.com, mike.leach@linaro.org,
James Clark <james.clark@arm.com>, Leo Yan <leo.yan@linaro.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h
Date: Thu, 3 Feb 2022 12:05:49 +0000 [thread overview]
Message-ID: <20220203120604.128396-2-james.clark@arm.com> (raw)
In-Reply-To: <20220203120604.128396-1-james.clark@arm.com>
This is a no-op change for style and consistency and has no effect on the
binary produced by gcc-11.
Signed-off-by: James Clark <james.clark@arm.com>
---
.../coresight/coresight-etm4x-core.c | 36 +++++--------------
drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++
drivers/hwtracing/coresight/coresight-priv.h | 5 +++
3 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index e2eebd865241..107e81948f76 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info)
etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
/* INSTP0, bits[2:1] P0 tracing support field */
- if (BMVAL(etmidr0, 1, 2) == 0b11)
- drvdata->instrp0 = true;
- else
- drvdata->instrp0 = false;
-
+ drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11);
/* TRCBB, bit[5] Branch broadcast tracing support bit */
- if (BMVAL(etmidr0, 5, 5))
- drvdata->trcbb = true;
- else
- drvdata->trcbb = false;
-
+ drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
/* TRCCOND, bit[6] Conditional instruction tracing support bit */
- if (BMVAL(etmidr0, 6, 6))
- drvdata->trccond = true;
- else
- drvdata->trccond = false;
-
+ drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
/* TRCCCI, bit[7] Cycle counting instruction bit */
- if (BMVAL(etmidr0, 7, 7))
- drvdata->trccci = true;
- else
- drvdata->trccci = false;
-
+ drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
/* RETSTACK, bit[9] Return stack bit */
- if (BMVAL(etmidr0, 9, 9))
- drvdata->retstack = true;
- else
- drvdata->retstack = false;
-
+ drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
/* NUMEVENT, bits[11:10] Number of events field */
- drvdata->nr_event = BMVAL(etmidr0, 10, 11);
+ drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT);
/* QSUPP, bits[16:15] Q element support field */
- drvdata->q_support = BMVAL(etmidr0, 15, 16);
+ drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP);
/* TSSIZE, bits[28:24] Global timestamp size field */
- drvdata->ts_size = BMVAL(etmidr0, 24, 28);
+ drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE);
/* maximum size of resources */
etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 3c4d69b096ca..2bd8ad953b8e 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -130,6 +130,23 @@
#define TRCRSR_TA BIT(12)
+/*
+ * Bit positions of registers that are defined above, in the sysreg.h style
+ * of _MASK, _SHIFT and BIT().
+ */
+#define TRCIDR0_INSTP0_SHIFT 1
+#define TRCIDR0_INSTP0_MASK GENMASK(1, 0)
+#define TRCIDR0_TRCBB BIT(5)
+#define TRCIDR0_TRCCOND BIT(6)
+#define TRCIDR0_TRCCCI BIT(7)
+#define TRCIDR0_RETSTACK BIT(9)
+#define TRCIDR0_NUMEVENT_SHIFT 10
+#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0)
+#define TRCIDR0_QSUPP_SHIFT 15
+#define TRCIDR0_QSUPP_MASK GENMASK(1, 0)
+#define TRCIDR0_TSSIZE_SHIFT 24
+#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)
+
/*
* System instructions to access ETM registers.
* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index ff1dd2092ac5..1452c6038421 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -36,6 +36,11 @@
#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
+/*
+ * Extract a field from a register where field is #defined in the form
+ * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
+ */
+#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT)
#define ETM_MODE_EXCL_KERN BIT(30)
#define ETM_MODE_EXCL_USER BIT(31)
--
2.28.0
next prev parent reply other threads:[~2022-02-03 12:06 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-03 12:05 [PATCH v2 00/15] Make ETM register accesses consistent with sysreg.h James Clark
2022-02-03 12:05 ` James Clark [this message]
2022-02-07 5:44 ` [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 " Anshuman Khandual
2022-02-07 19:02 ` Mathieu Poirier
2022-02-08 15:04 ` Suzuki K Poulose
2022-02-09 9:32 ` Mike Leach
2022-02-25 16:28 ` James Clark
2022-02-08 11:36 ` Mike Leach
2022-02-03 12:05 ` [PATCH v2 02/15] coresight: Make ETM4x TRCIDR2 " James Clark
2022-02-03 12:05 ` [PATCH v2 03/15] coresight: Make ETM4x TRCIDR3 " James Clark
2022-02-03 12:05 ` [PATCH v2 04/15] coresight: Make ETM4x TRCIDR4 " James Clark
2022-02-03 12:05 ` [PATCH v2 05/15] coresight: Make ETM4x TRCIDR5 " James Clark
2022-02-03 12:05 ` [PATCH v2 06/15] coresight: Make ETM4x TRCCONFIGR " James Clark
2022-02-03 12:05 ` [PATCH v2 07/15] coresight: Make ETM4x TRCEVENTCTL1R " James Clark
2022-02-07 19:03 ` Mathieu Poirier
2022-02-03 12:05 ` [PATCH v2 08/15] coresight: Make ETM4x TRCSTALLCTLR " James Clark
2022-02-03 12:05 ` [PATCH v2 09/15] coresight: Make ETM4x TRCVICTLR " James Clark
2022-02-03 12:05 ` [PATCH v2 10/15] coresight: Make ETM3x ETMTECR1 " James Clark
2022-02-03 12:05 ` [PATCH v2 11/15] coresight: Make ETM4x TRCACATRn " James Clark
2022-02-03 12:06 ` [PATCH v2 12/15] coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn " James Clark
2022-02-03 12:06 ` [PATCH v2 13/15] coresight: Make ETM4x TRCSSPCICRn " James Clark
2022-02-03 12:06 ` [PATCH v2 14/15] coresight: Make ETM4x TRCBBCTLR " James Clark
2022-02-03 12:06 ` [PATCH v2 15/15] coresight: Make ETM4x TRCRSCTLRn " James Clark
2022-02-08 18:58 ` Mathieu Poirier
2022-02-07 5:51 ` [PATCH v2 00/15] Make ETM " Anshuman Khandual
2022-02-07 10:03 ` James Clark
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