From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26D9BC4332F for ; Thu, 3 Feb 2022 20:33:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354671AbiBCUdp (ORCPT ); Thu, 3 Feb 2022 15:33:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354328AbiBCUci (ORCPT ); Thu, 3 Feb 2022 15:32:38 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 220C0C0613DC; Thu, 3 Feb 2022 12:32:18 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D8ABAB835A9; Thu, 3 Feb 2022 20:32:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7EC1CC340EB; Thu, 3 Feb 2022 20:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643920335; bh=wLEOq3urc55jW+NWAQ6xw+F5yHn5AdI27akNuSKT6lI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Qekoc+rwlFAQGKSuJ8PuhpJ3iIcEz/ILHG7rO9JgVbZs/TXB0SJhkg2WA2XRIT5eg 2h9wqckVn4uN+Bh43FnFYkPRIzncnTlgi+4WeWuVLfO/3+ZqQjhs4gAdXz0urmoyQl FNDYW0s4xBdCPpIrlJ2i6zn5Kv0IfKJLPAVrRjdPquK2A9NBXOgPPvucWvXRn/YCT4 rKOD9Pf/EPUDXlMcmJweLmkIIkCYfJGqO19j8JnnpS0r+ToKert4CwHDmZG0mkwIpl MkyAhsZCBzqe+1etUFZ25WzZs7yCu6FcloTBXfldqS8T+tgafNEbtI7EJ5YhRQ3Ymy t1sr4Sb6rYVVw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Suzuki Poulose , linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Sasha Levin , marcan@marcan.st Subject: [PATCH AUTOSEL 5.16 46/52] arm64: Add Cortex-A510 CPU part definition Date: Thu, 3 Feb 2022 15:29:40 -0500 Message-Id: <20220203202947.2304-46-sashal@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220203202947.2304-1-sashal@kernel.org> References: <20220203202947.2304-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anshuman Khandual [ Upstream commit 53960faf2b731dd2f9ed6e1334634b8ba6286850 ] Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Suzuki K Poulose Acked-by: Catalin Marinas Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/1643120437-14352-2-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 657eeb06c7847..999b9149f8568 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,7 @@ #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 @@ -116,6 +117,7 @@ #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) +#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) -- 2.34.1